41.
    发明专利
    未知

    公开(公告)号:DE60223636T2

    公开(公告)日:2008-10-30

    申请号:DE60223636

    申请日:2002-09-13

    Inventor: WUIDART LUC

    Abstract: A portable means of identification (10) has a fingerprint captor (1) which is associated with an extraction and digitization unit (12). An identifier (16) which is drawn from a system of physical parameters (17) such as a time constant relating to the captor is combined with the fingerprint data and scrambled (15). The result is compared (13) with a reference model (14) to give an identification An Independent claim is also included for: A portable identifying equipment which uses the captor physical parameter identifier

    44.
    发明专利
    未知

    公开(公告)号:DE69835328T2

    公开(公告)日:2007-08-23

    申请号:DE69835328

    申请日:1998-11-20

    Abstract: The fluorescent lamp (T) has a bridge rectifier (10) for the incoming low frequency mains supply. The rectifier output (11, 12) is bridged by a switch (M) driven at high frequency to provide a chopped current. Inductors (40, 41) are connected in series in two arms of the bridge and are connected by a switch (36, 37, 38) to form an energy recovery circuit.

    45.
    发明专利
    未知

    公开(公告)号:DE60125088T2

    公开(公告)日:2007-07-12

    申请号:DE60125088

    申请日:2001-05-11

    Inventor: WUIDART LUC

    Abstract: A terminal for generating a high-frequency electromagnetic field by an oscillating circuit, adapted to cooperating with at least one transponder when the transponder enters this field, and a method for establishing a communication between the devices, including circuitry for regulating the signal phase in the oscillating circuit with respect to a reference value and circuitry for evaluating, based on a measurement of the current in the oscillating circuit, the minimum number of transponders present in the field.

    47.
    发明专利
    未知

    公开(公告)号:FR2846463A1

    公开(公告)日:2004-04-30

    申请号:FR0213458

    申请日:2002-10-28

    Inventor: WUIDART LUC

    Abstract: The monotonic counter is implemented as an integrated circuit where each counting bit (B1,B2,B3,B4) is provided by a memory cell (11) containing at least one memory element constituted of a resistor of polycrystalline silicon which is programmable by an irreversible decrease of its resistance. The counter also comprises a circuit (30) for decoding the states of memory cells for obtaining the resultant count. The programming of the resistor of polycrystalline silicon is by a temporary passage of a constraint current which is higher than a current for which the resistance has the maximum value. Each counting cell comprises a programming resistor connected between a first supply terminal and a differential read terminal, and at least one programming interrupter connecting the read terminal to a second supply terminal. The programming resistor is in the form of two resistors of polycrystalline silicon which are identical in size and doping level. The counter also comprises a circuit for programming control (CTRL) of each counting cell and for providing control signals to each programming interrupter. The four bits (B1,B2,B3,B4) are arranged in a line of cells (11) which are all read simultaneously for obtaining the outputs (S1,S2,S3,S4). The number of cells in the state 0 and the state 1 is detected by the decoding circuit (30) which has five counting outputs (C0,C1,C2,C3,C4) linked to the four inputs by a NAND gate (31), nine AND gates (32,33,34,35,36,37,38,39,40), two OR gates (41,42), and a NOR gate (43).

    50.
    发明专利
    未知

    公开(公告)号:FR2823341B1

    公开(公告)日:2003-07-25

    申请号:FR0104585

    申请日:2001-04-04

    Abstract: The invention concerns an identification method and circuit ( 1 ) of the network type of parameters contained in an integrated circuit chip, comprising a single input terminal ( 2 ) for applying a signal (E) triggering an identification, the output terminals ( 3 1 , 3 2 , 3 i-1 , 3 i , 3 n-1 , 3 n ) adapted to deliver a binary identifying code (B 1 , B 2 , B i-1 , B i , B n-1 , B n ), first electrical paths P 1 , P 2 , P i , P n ), individually connecting said input terminal to each output terminal, and means ( 4, 5 1 , 5 2 , 5 i , 5 n ) for simultaneously integrating the binary states present in output of the electrical paths, each path inputting a delay sensitive to technological dispersions and/or of the integrated circuit fabrication method.

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