公开(公告)号：US11543842B2

公开(公告)日：2023-01-03

申请号：US16803942

申请日：2020-02-27

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Mirko Dondini ,  Daniele Mangano ,  Riccardo Condorelli

IPC: G05F1/00 ,  G05F1/575 ,  G05B19/042 ,  G06F13/40 ,  H03B5/32 ,  H03K19/17736

Abstract: An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.

公开(公告)号：US11533019B2

公开(公告)日：2022-12-20

申请号：US17180752

申请日：2021-02-20

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Benoit Marchand ,  Hamilton Emmanuel Querino De Carvalho ,  Achraf Dhayni ,  Daniele Mangano

IPC: H04B1/04 ,  H03F3/24 ,  H03B5/36 ,  H03L1/02 ,  H03L7/099 ,  G06F1/10

Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.

公开(公告)号：US20210278868A1

公开(公告)日：2021-09-09

申请号：US16810639

申请日：2020-03-05

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Michel Cuenca ,  Bruno Gailhard ,  Daniele Mangano

IPC: G05F1/56

Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.

公开(公告)号：US10985736B2

公开(公告)日：2021-04-20

申请号：US16894640

申请日：2020-06-05

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Daniele Mangano ,  Roland Van Der Tuijn ,  Pasquale Butta′

IPC: H03K3/01 ,  H03K17/20 ,  G06F1/24 ,  H03K19/20

Abstract: An embodiment device comprises a processing circuit and IP circuitry coupled to a power supply line, wherein the IP circuitry has an IP circuitry supply threshold for IP circuitry operation. A supply monitor circuit is coupled to the power supply line to sense the voltage on the power supply line and to switch the processing circuit to a low-power mode as a result of a drop in the voltage on the power supply line. The supply monitor circuit comprises a threshold setting node and is configured to be deactivated as a result of the voltage on the power supply line dropping below a deactivation threshold level set at the threshold setting node. A threshold setting circuit is configured to apply to the threshold setting node of the supply monitor circuit the IP circuitry supply threshold as a result of the processing circuit being in the low-power mode.

公开(公告)号：US10168443B2

公开(公告)日：2019-01-01

申请号：US14835935

申请日：2015-08-26

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Daniele Mangano ,  Riccardo Condorelli

IPC: G01V3/10 ,  H03K17/95

Abstract: A system for interfacing an LC sensor includes a starter configured to selectively start an oscillation of the LC sensor. The system also includes an analog peak detector configured to determine a signal (Vpeak) being indicative of a peak voltage of the oscillation of the LC sensor and a detector configured to determine a state of the LC sensor as a function of the signal (Vpeak) determined by the analog peak detector.

公开(公告)号：US09959226B2

公开(公告)日：2018-05-01

申请号：US14841522

申请日：2015-08-31

Applicant: STMicroelectronics S.R.L.

Inventor： Daniele Mangano ,  Mirko Dondini ,  Salvatore Pisasale

IPC: G06F13/28 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/067 ,  G06F13/4059 ,  G06F2213/0038

Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.

公开(公告)号：US09823965B2

公开(公告)日：2017-11-21

申请号：US15080307

申请日：2016-03-24

Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.R.L.

Inventor： Daniele Mangano ,  Michele Alessandro Carrano ,  Gaetano Di Stefano ,  Antonin Fried

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1044 ,  G11C29/52

Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.

公开(公告)号：US20170187380A1

公开(公告)日：2017-06-29

申请号：US15458692

申请日：2017-03-14

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Marco Rosselli ,  Daniele Mangano ,  Riccardo Condorelli

IPC: H03K19/00 ,  H03K19/173 ,  G06F15/78 ,  H03K19/177

CPC classification number: H03K19/0008 ,  G06F15/7867 ,  G06F2209/507 ,  H03K19/1737 ,  H03K19/1776

Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.

公开(公告)号：US20170139461A1

公开(公告)日：2017-05-18

申请号：US14943472

申请日：2015-11-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Roberto LAROSA ,  Daniele Mangano ,  Riccardo Condorelli ,  Giulio Zoppi ,  Natale Aiello

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3206 ,  G06F1/26

Abstract: An electronic device may include a transducer configured to generate an electrical output responsive to an input, and a data storage element configured to change state responsive to the transducer. The electronic device may include a power circuit configured to turn on and supply power responsive to the data storage element changing state, and a processing circuit configured to be powered by the power circuit.

公开(公告)号：US09471521B2

公开(公告)日：2016-10-18

申请号：US14278403

申请日：2014-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Daniele Mangano ,  Giuseppe Falconeri

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.

Abstract translation: 通信系统被布置为将多个传输电路与互连网络接口。 每个传输电路产生读请求和/或写请求。 通信系统包括独立于互连网络的通信协议操作的第一电路。 特别地，第一电路包括：a）对于每个传输电路，配置用于从各个传输电路接收读取请求和/或写入请求的通信接口，b）分配电路，被配置为将读取请求 和/或将从所述传输电路接收的请求写入传输段，以及c）被配置为经由所述传送段的交织操作生成一系列段的交织电路。 通信系统还包括第二电路，其被配置为根据互连网络的协议将一系列段的传输段转换成数据包，并将数据包发送到互连网络。