公开(公告)号：US12255244B2

公开(公告)日：2025-03-18

申请号：US18171502

申请日：2023-02-20

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Minhyun Lee ,  Minsu Seol ,  Ho Won Jang ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

Abstract: Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

公开(公告)号：US12199129B2

公开(公告)日：2025-01-14

申请号：US17313464

申请日：2021-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Hyeonjin Shin

IPC: H01L27/146 ,  H04N23/11

Abstract: An image sensor includes a visible light sensor portion and an infrared sensor portion arranged on the visible light sensor portion. The visible light sensor portion includes a first sensor layer and a first signal wiring layer, wherein a plurality of visible light sensing elements are arrayed in the first sensor layer and the first signal wiring layer is configured to process a signal output from the first sensor layer. The infrared sensor portion includes a second sensor layer in which a plurality of infrared sensing elements are arrayed, and a second signal wiring layer configured to process a signal output from the second sensor layer. The infrared sensor portion and the visible light sensor portion form a single monolithic structure which is effective in obtaining high resolution.

公开(公告)号：US12193235B2

公开(公告)日：2025-01-07

申请号：US17537984

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek Oh ,  Hyeyoung Kwon ,  Taein Kim ,  Gukhyon Yon ,  Minhyun Lee

IPC: H10B43/27

Abstract: A nonvolatile memory device includes a channel layer, a plurality of gate electrodes and a plurality of separation layers spaced apart from the channel layer and alternately arranged, a charge trap layer between the gate electrodes in the channel layer, and a charge blocking layer between the charge trap layer and the gate electrode.

公开(公告)号：US12087818B2

公开(公告)日：2024-09-10

申请号：US17967200

申请日：2022-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Hyeonjin Shin

IPC: H01L29/10 ,  H01L29/36 ,  H01L29/423

CPC classification number: H01L29/1033 ,  H01L29/36 ,  H01L29/4232

Abstract: A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer.

公开(公告)号：US11985910B2

公开(公告)日：2024-05-14

申请号：US17836435

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun Lee ,  Dovran Amanov ,  Renjing Xu ,  Houk Jang ,  Haeryong Kim ,  Hyeonjin Shin ,  Yeonchoo Cho ,  Donhee Ham

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H10B63/80 ,  H10N70/24 ,  H10N70/8416

Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.

公开(公告)号：US11575011B2

公开(公告)日：2023-02-07

申请号：US17515713

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd. ,  THE UNIVERSITY OF CHICAGO ,  Center for Technology Licensing at Cornell University

Inventor： Minhyun Lee ,  Jiwoong Park ,  Saien Xie ,  Jinseong Heo ,  Hyeonjin Shin

IPC: H01L29/15 ,  H01L29/10

Abstract: Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

公开(公告)号：US11532709B2

公开(公告)日：2022-12-20

申请号：US17203010

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Minsu Seol ,  Yeonchoo Cho ,  Hyeonjin Shin

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/423

Abstract: A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.

公开(公告)号：US11462477B2

公开(公告)日：2022-10-04

申请号：US17082494

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin Shin ,  Minhyun Lee ,  Changseok Lee ,  Hyeonsuk Shin ,  Seokmo Hong

IPC: H01L23/532 ,  H01L23/522

Abstract: An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

公开(公告)号：US11424186B2

公开(公告)日：2022-08-23

申请号：US17082530

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin Shin ,  Minhyun Lee ,  Changseok Lee ,  Kyung-Eun Byun ,  Hyeonsuk Shin ,  Seokmo Hong

IPC: H01L23/532 ,  H01L23/522 ,  H01L27/108

Abstract: A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

公开(公告)号：US10811604B2

公开(公告)日：2020-10-20

申请号：US16144257

申请日：2018-09-27

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Minhyun Lee ,  Seongjun Park ,  Hyunjae Song ,  Hyeonjin Shin ,  Kibum Kim ,  Sanghun Lee ,  Yunho Kang

IPC: H01L45/00 ,  H01L21/768 ,  G11C13/00

Abstract: A nonvolatile memory apparatus includes a first electrode, a second electrode separated from the first electrode, a resistive-change material layer provided between the first electrode and the second electrode and configured to store information due to a resistance change caused by an electrical signal applied through the first electrode and the second electrode, and a diffusion prevention layer provided between the first electrode and the resistive-change material layer and/or between the second electrode and the resistive-change material layer and including a two-dimensional (2D) material having a monolayer thickness of about 0.35 nm or less.