Abstract:
A sequence controller (18) for controlling load/reset sequences for a spatial light modulator (15). The sequence controller has a program memory (41) for storing load instructions and reset instructions. A load control processor (42) executes load instructions. A reset control processor (43) executes reset instructions. The two processors (42, 43) operate independently except for synchronization.
Abstract:
A method and system for accentuating intense white display areas in sequential DMD video systems includes generating a special signal for each pixel that indicates whether to boost the intensity of that pixel in all colors. The method further includes enabling the mirrors to be turned on during times of color boundary of the color wheel such that DMD with mirrors receives different mixes of color light that are integrated together to produce intense white. The system may include degamma lookup tables for each color. The degamma lookup tables are augmented when the special signal is generated.
Abstract:
A method for causing a micromechanical spatial light modulator to display data for a period less than its settling time. The modulator elements receive a first pulse (40) that causes them to release from their previous state, a bias voltage is removed and reapplied, allowing the elements to move to the unaddressed state, and then the elements receive a second pulse (46). After receiving a second pulse, the elements assume an unaddressed state. In one embodiment, new address data is loaded during this unaddressed state, after which a bias is reapplied causing them to achieve the state corresponding to the new state. In another embodiment, the previous addresses are cleared during the unaddressed state, forcing the elements into an OFF state. In either embodiment, a reset pulse may be applied after either the load or clear step.
Abstract:
A data converter (13) for providing data for secondary images in a video display system (10). One embodiment (FIGURE 2) provides data for a staggered pixel array, by using an A/D converter (23) to sample the data at a rate of 2/n(h) times the sample rate of the main image, where 1/n(h) is the horizontal scaling factor. A multiplexer (24) selects between two different sample patterns. Another embodiment (FIGURE 3) provides data for progressively scanned secondary images by selecting 2/n(v) times the number of lines per input field, where 1/n(v) is the vertical scaling factor.
Abstract:
A system for handling special television video features digitally. The system receives incoming broadcast video into a switch (106). The switch allows the viewer to select a main channel and at least one auxiliary channel for viewing as a special feature, if the viewer does not want to view only the main channel for that particular special feature. The main video channel data is processed by a scan converter(216) to convert it from interlaced to progressive scan. A logic device(212) handles the auxiliary channel data to format it into the selected special feature and inputs that data to the scan converter(216) such that the special feature appears in the proper place relative to the main channel image.
Abstract:
A data reformatter/frame memory (112) for efficiently orthogonally reordering a digital data stream. The disclosed reformatter/frame memory (112) is typically used in conjunction with a display device (124) for displaying the digital data, and a display controller (132) for coordinating the transfer of data between the reformatter/frame memory (112) and the display device (124). According to one embodiment, a data reformatter for a video display system includes at least one reformatter memory plane. The memory plane comprises an input bus, an m x n array of memory cells in communication with the input bus, and an m-bit-wide output bus. The array of memory cells receives and stores m n-bit-wide input data words and outputs n m-bit-wide output data words. Each of the m-bit-wide output data words is comprised of one bit from each of the m n-bit-wide input data words.
Abstract:
A memory (15) for a digital display system (10) having a spatial light modulator (SLM) (16) that displays data in bit-plane format. The memory (15) has control means (25) for row random access. It also has a set of input registers (31) and two sets of output registers (32), (33). The input registers (31) receive pixel data before it has been processed. The memory (15) delivers this data back to a processor (14) for processing via a first set of output registers (32). After processing, the input registers (31) receive pixel data that has been fully processed and is ready for display. The second set of output registers (33), controlled at their input or output by a bit selector (37), delivers bit-planes of data to the SLM (16).
Abstract:
A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexer (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stored in first first in-first out buffer memories (34) and (36), respectively. Multiplexer (38) combines one line from first first in-first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.