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公开(公告)号：JPH02149023A
公开(公告)日：1990-06-07
申请号：JP30268288
申请日：1988-11-30
Applicant: TOSHIBA CORP
Inventor： SERIZAWA MUTSUMI , MURAKAMI JUNZO
Abstract: PURPOSE:To improve transmission quality by providing the calculating means and the synthesizing means of branch-metric and a viterbi algorithm operating means, and calculating the branch-metric from a received signal, and synthesizing those. CONSTITUTION:The branch-metric calculating parts 61, 63 calculate the branch- metric of detection signals obtained respectively by orthogonal detecting parts 55, 57 according to a reference signal generated from a reference signal generating part 59. Adding parts 65a, 65b, 65c... add the corresponding branch-metric outputted respectively from the branch-metric calculating parts 61, 63. The viterbi algorithm operating part 67 operates viterbi algorithm from the output signals of the adding parts 65a, 65b, 65c. Accordingly, since the non-negative branch-metric to show the probability of a reception signal is added by the adding part after being calculated, delayed waves never cancel each other, and the transmission quality is made favorable.
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公开(公告)号：JPH021644A
公开(公告)日：1990-01-05
申请号：JP14241188
申请日：1988-06-09
Applicant: TOSHIBA CORP
Inventor： SERIZAWA MUTSUMI
IPC: H04L12/28
Abstract: PURPOSE:To prevent collision in a transmission line by permitting respective base stations to calculate likelihood showing certainty in radio signals received from slave stations, to decide a time based on the likelihood and to transmit the signals to a master station through the transmission line after a prescribed time. CONSTITUTION:The signals from the slave stations 21, 23 and 25 are received in respective base stations 11, 13 and 15. The reception signals are demodulated in a demodulator 37 and are supplied to a likelihood calculation circuit 35. Likelihood showing the certainty of a demodulation signal is calculated, the time based on the likelihood is waited for, and transmission is executed only when the transmission line 17 is in an used state. Thus, transmission signals from the base stations 11 and 13 are prevented from colliding. A waiting time corresponding to likelihood calculated in the circuit is decided in a time decision means provided in a LAN node processor 33. When likelihood is large, the waiting time is set short, and it is set long when likelihood is small. Thus, the base station which has received the packet signal of largest likelihood transmits the signal to the transmission line 17 fastest and the master station 20 can receive it at the largest probability.
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公开(公告)号：JPH01202036A
公开(公告)日：1989-08-15
申请号：JP2563788
申请日：1988-02-08
Applicant: TOSHIBA CORP
Inventor： TSURUMI HIROSHI , SERIZAWA MUTSUMI , YOKOI TOKIHIKO
IPC: H04B7/26
Abstract: PURPOSE:To form a system with high power efficiency by allowing a base station to detect the position of a slave station to be communicated and to turn directivity to the existence direction of the slave station to communicate with the slave station. CONSTITUTION:The position of the slave station is previously grasped by the base station side and the directivity is turned to the direction to execute communication between the slave station and the base station. Namely, plural slave stations 3-17 can execute communication with the base station in a range at which radio waves can arrive. The base station 1 detects the position of the slave station 3 to be communicated by a position detecting means. The directivity is turned to the direction of the position of the slave station 3 obtained by the position detecting means by a directivity control means to communicate with the slave station 3. Since the directivity can be turned to all directions, necessary transmission power can be sharply reduced by the base station 2.
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公开(公告)号：JPS63215246A
公开(公告)日：1988-09-07
申请号：JP4946787
申请日：1987-03-04
Applicant: TOSHIBA CORP
Inventor： SERIZAWA MUTSUMI
IPC: H04L27/22
Abstract: PURPOSE:To attain the establishment of synchronization in a short time even at the change in the transmission speed by revising the quantity being the result of normalizing a value stored in a tentative storage in a synchronizing detection loop, that is, the frequency offset in the synchronizing loop by means of a sampling clock at a multiple of 1/2 in multiplying a sampling clock frequency by a multiple of (a). CONSTITUTION:When a ground station B receives a multiple access speed digital signal sent from a ground station A, the station A sends a signal in any of transmission speeds, e.g., f1, af1, a f1.... Moreover, the station B converts down a transmission signal into a base band complex number signal (two orthogonal signals), samples the signal by using a frequency twice the transmission speed to apply synchronizing detection. In changing the transmission speed to, e.g., a multiple of (a), the stored value of a loop filter register of a demodulator is controlled to be made to a multiple of 1/a. The control is applied similarly by varying the transmission speed and the channel. That is, since the value stored in the loop filter register is almost due to an up-converter, a down- converter and a frequency converter on a satellite, even when the channel is revised, almost no fluctuation is given to the frequency error.
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公开(公告)号：JPS62142441A
公开(公告)日：1987-06-25
申请号：JP28400785
申请日：1985-12-17
Applicant: TOSHIBA CORP
Inventor： SERIZAWA MUTSUMI , SUZUKI HIDEO
Abstract: PURPOSE:To reduce the entire hardware without requiring multiplication by applying signal processing for the phase error detection of a recovery carrier and/or recovery clock after a digital signal series being amplitude information is converted into phase information. CONSTITUTION:A couple of digital signal series being in orthogonal phase relation are inputted to signal input terminals 1, 2 and inputted to a conversion circuit 3. The conversion circuit 3 outputs the phase information corresponding to the combination of the amplitude as a digital signal. The output phase information of the conversion circuit 3 is compared with the information of recovered carrier phase at a subtractor 4, the phase component of the recovered carrier is eliminated and the periodic constant string is added by an adder 6 and a switch 7 changed over at a period T (T; symbol length) and the module pi is taken in a block 8, the result is inputted to a loop filter 9 and the recovered carrier phase error signal being a DC component is extracted. The output of the loop filter 9 is given to a digital VCO 10 as a control input and an accumulating adder 12 outputs recovered carrier phase information and gives it to the subtractor 4.
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Patent Agency Ranking
公开(公告)号：JPS621335A
公开(公告)日：1987-01-07
申请号：JP13890285
申请日：1985-06-27
Applicant: TOSHIBA CORP
Inventor： SERIZAWA MUTSUMI , TAKAHASHI HIDEHIRO
Abstract: PURPOSE:To apply highly accurate control to a high speed phase synchronous system by obtain a beat signal between an input signal and an oscillator output having a low frequency adapted of the digital signal processing technology, and using a forecast signal to generate a control signal. CONSTITUTION:An input signal is inputted to a terminal 5. The signal is fed to a beat signal generating circuit 2 together with the output of the oscillator 3. In the circuit 2, a beat signal 7 between the synchronizing signal and the oscillator output is generated and outputted. The output of the circuit 2 is inputted to a forecast circuit 4 to detect the frequency and the phase of the input signal and the beat signal at an optional time T is forecasted based on the phase of the detected frequency and its forecast waveform is outputted to a terminal 8.
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公开(公告)号：JPS61274458A
公开(公告)日：1986-12-04
申请号：JP11592585
申请日：1985-05-29
Applicant: TOSHIBA CORP
Inventor： SERIZAWA MUTSUMI , SUZUKI HIDEO
Abstract: PURPOSE:To separate and extract phase error information in high speed by converting an input digital signal series into phase information and applying algebraic processing based on the result of discrimination with respect to the transition state of the phase information. CONSTITUTION:A signal in a couple of orthogonal phase relations obtained by separating a digital modulation signal into two orthogonal signals at the reception side is inputted to terminals 1, 2, and converted into a digital signal series by A/D converters 3, 4 and inputted to a conversion table 5. An output signal of the conversion table 5 is inputted to a subtractor 6, where a carrier phase component is eliminated to form a carrier phase synchronous detection output, which is inputted to a transition state discrimination circuit 7 and a separation circuit 8. The separation circuit 8 separates the output signal of the subtractor 6 into, e.g., recovered carrier phase error information and sampling clock phase error information at the A/D converters 2, 3 based on the result of discrimination of the transition state discrimination circuit 7.
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公开(公告)号：JPS61274457A
公开(公告)日：1986-12-04
申请号：JP11592485
申请日：1985-05-29
Applicant: TOSHIBA CORP
Inventor： SERIZAWA MUTSUMI , SUZUKI HIDEO
Abstract: PURPOSE:To realize a detection of high accuracy by detecting a phase difference using a phase locked circuit synchronized with a phase change component which depends upon each of different transmission data patterns with each other in an inputted digital modulating signal. CONSTITUTION:The first phase locked circuit 7 is synchronized with a phase component which depends upon the first transmission data pattern in the inputted digital modulating signal out of phase informations outputted from a conversion table 5 and the second phase locked circuit 8 is synchronized with the second phase change component synchronized with the second transmission data pattern in the inputted digital modulating signal. A phase error arithmetic circuit 9 calculates the phase error from the output signals of these first and second phase locked circuits 7 and 8. The phase locked circuits 7 and 8, after a phase lock is once settled, operate in the same manner so that the same signal is inputted to these circuits. Therefore, it is possible to detect a clock phase error accurately than ever.
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49.发明专利
公开(公告)号：JP2004328786A
公开(公告)日：2004-11-18
申请号：JP2004173865
申请日：2004-06-11
Applicant: Toshiba Corp , 株式会社東芝
Inventor： TAKAGI MASAHIRO , KAMAGATA EIJI , KATO NORIYASU , TSUNODA KEIJI , NAKAKITA KUMIKO , NOUJIN KATSUYA , SERIZAWA MUTSUMI
IPC: H04L12/66 , H04L12/70 , H04M3/00 , H04W28/04 , H04W36/12 , H04W36/22 , H04W80/04 , H04W80/06 , H04L12/56 , H04Q7/22 , H04Q7/24 , H04Q7/26 , H04Q7/30 , H04Q7/38
Abstract: PROBLEM TO BE SOLVED: To setup transport layer connection between a wired terminal and a wireless terminal in a form suitable for an application without changing transport layer implementation for a terminal connected to a wired network, and to provide a highly reliable gateway device which improves the performance of communication which uses the transport layer connection. SOLUTION: In the gateway system providing trunk connection for the wireless network and the wired network, it is determined whether the transport layer connection between the terminals is split into transport layer protocol connection for communication with the wireless network and transport layer protocol connection for communication with the wired network to be set or is carried without going through the split connection according to an application type known from a transport layer protocol data unit which requires the transport layer connection setting between a connection terminal for the wireless network and a connection terminal for the wired network. COPYRIGHT: (C)2005,JPO&NCIPI
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公开(公告)号：JP2003179981A
公开(公告)日：2003-06-27
申请号：JP2002350527
申请日：2002-12-02
Applicant: TOSHIBA CORP
Inventor： TOSHIMITSU KIYOSHI , SERIZAWA MUTSUMI , NOUJIN KATSUYA , KAMAGATA EIJI , NAKAJIMA NOBUYASU
Abstract: PROBLEM TO BE SOLVED: To provide control procedures for efficiently performing information transmission in a wireless communication system having narrow-band uplink and downlink wireless channels and a wide-band downlink wireless channel. SOLUTION: The wireless communication system consists of a narrow-band wireless base station having a narrow-band transmission/reception means for information transmission a wide-band wireless base station having a storage means for storing information destined to a wireless terminal and a wide-band transmission means provided for information transmission including the information, destined to the wireless terminal, and stored in this storage means and a wireless terminal having a narrow-band transmission/reception means for transmitting/receiving information with the narrow-band wireless base station and a wide-band receiving means for receiving the information from the wide- band wireless base station. The system has a function of deleting the information, destined to the wireless terminal, stored in the storage means if at least either the information transmission from the wide-band wireless base station to the wireless terminal or the information transmission between the narrow- band wireless base station and the wireless terminal is disabled. COPYRIGHT: (C)2003,JPO
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