公开(公告)号：JP2000261511A

公开(公告)日：2000-09-22

申请号：JP6458999

申请日：1999-03-11

Applicant: TOSHIBA CORP

Inventor： NODA ATSUSHI ,  TANAKA SHUICHI

IPC: H03M13/00 ,  H04L27/00 ,  H04L27/34

Abstract: PROBLEM TO BE SOLVED: To attain conversion of a signal series suitable for digital transmission attended with error control by even on the occurrence of an error in excess of an error correction capability of an error correction code in a digital transmission signal. SOLUTION: This digital transmission system adopts 27 (=128) QAM (quadrature amplitude modulation) demodulation system and employs a reed Solomon code on a GF (28) for its error correction system. The transmitter side applies 8-7 conversion to a transmission digital signal after error correction coding and applies modulation the 8-7 converted signal, and the receiver side applies 7-8 conversion to a received digital signal after demodulation and then applies error correction decoding to the 7-8 converted signal. Furthermore, in the case of 8-7 conversion and the 7-8 conversion as above, the transmitter side does not convert a signal of 1-series 8-bit outputted from transmission digital processing units TPDU 11, 21 directly into a signal of 1-series 7-bit but applies 8-1 conversion to the 8-bit signal after 1-7 conversion and the receiver side conducts 7-1 conversion after 8-1 conversion.

公开(公告)号：JPH0537574A

公开(公告)日：1993-02-12

申请号：JP19144891

申请日：1991-07-31

Applicant: TOSHIBA CORP

Inventor： FUJII YASUYUKI ,  TANAKA SHUICHI

IPC: H03M13/00 ,  H04L27/00 ,  H04L27/18

Abstract: PURPOSE:To allow the circuit to cope with a speed increase of a signal even when the speed is set to a multiple of (m) of the operation limit speed of an elastic storage element used for a speed conversion means. CONSTITUTION:A coder of a digital microwave radio equipment of the 16QAM modulation system employs the GF(2 ) (63,59,4) reed Solomon code. Then an input signal given through a sum logic circuit 32 is subject to parallel conversion into 6 series by serial parallel conversion circuits 331-334 and speed conversion circuits 341-344 employing elastic storage elements apply speed conversion to the signal subject to parallel conversion. The signal subject to error correction coding by error correction coding circuits 351-354 and the signal of m-series is subject to serial conversion to one series by parallel serial conversion circuits 371-374.

公开(公告)号：JPH04150526A

公开(公告)日：1992-05-25

申请号：JP27325290

申请日：1990-10-15

Applicant: TOSHIBA CORP

Inventor： TANAKA SHUICHI

IPC: H04B7/08

Abstract: PURPOSE:To correct transmission time difference between a main receiving system and an auxiliary receiving system through simple configuration not using a coaxial cable by providing the receiving system of longer reception processing time required for inputting its output to a synthesizing device between the main receiving system and the auxiliary receiving system with a specified band pass filter. CONSTITUTION:The receiving system whose reception processing time required for inputting its output to the synthesizing device 5 is longer between the main receiving system 2 and the auxiliary receiving system 4 is provided with the band pass filter 42d in which pass band width B in the case of fall by 3 dB is in the relation of B 1.36/t where (t) is the time difference between the reception processing time of the main receiving system 22 and the reception processing time of the auxiliary receiving system 42. Thus, the correction of the transmission time difference between the main receiving system and the auxiliary receiving system can be executed by the comparatively small band pass filter, and the coaxial cable need not be used.

公开(公告)号：JPH0397338A

公开(公告)日：1991-04-23

申请号：JP23284089

申请日：1989-09-11

Applicant: TOSHIBA CORP ,  NIPPON TELEGRAPH & TELEPHONE

Inventor： OYA YASUNORI ,  TANAKA SHUICHI ,  YOSHIKAWA TATSUO

IPC: H04L27/38

Abstract: PURPOSE:To always stably detect a pseudo code error with no adjustment and to attain proper switching control with simple constitution and handling by detecting the pseudo code error through the logical processing of an identification signal composed of a binary digital signal outputted from an identifying device. CONSTITUTION:A 2 value orthogonal amplitude modulation wave is bisected by a divider 13, a 2 value demodulation signal obtained through synchronization detectors 11a, 11b, low pass filters 13a, 13b and operational amplifiers 14a, 14b is introduced respectively to identifying devices 15a, 15b at in-phase and orthogonal phase each and the identification output is subjected to logical processing to obtain a demodulation data. A pseudo code error detection circuit 30 applies exclusive OR processing to adjacent bits from high-order (n+1)th bit to at least high-order (n+3)th bit in the identification output of at least one identification device among the identifying devices, and applies prescribed AND or OR processing to each output of the exclusive OR processing and outputs its output as a detection signal of the pseudo code error.

公开(公告)号：JPH02249379A

公开(公告)日：1990-10-05

申请号：JP6932589

申请日：1989-03-23

Applicant: TOSHIBA CORP

Inventor： TANAKA SHUICHI

IPC: H04N5/92 ,  G11B27/00 ,  G11B27/10

Abstract: PURPOSE:To retrieve a desired screen in a short time without giving a load onto a tape and a tape running system by dividing each picture data constituting N sets of screens into sub screen signals 1-n and creating in total N sets of screens to constitute one screen with N kinds of sub screen signal units. CONSTITUTION:A sub screen split means 22 samples a one screen data to be recorded in the unit of 1/n sub screen to split it into (n) kinds of sub screen signals 1-n. A screen edit means 22 uses a sub screen split means 22 to divide each screen data constituting N sets of screens 1-N into sub screen signals 1/n respectively to create in total N sets of screens to constitute one screen in the unit of N kinds of sub screen signals. A recording means 40 records a created each screen onto a recording medium 39 sequentially and a reproduction means 40 reproduces one screen of a recorded tape 39 and outputs the obtained reproducing signal in a prescribed order as the picture data. Thus, the desired screen is retrieved in a short time without giving load onto the magnetic tape 39 and the magnetic tape running system.

公开(公告)号：JPH0265424A

公开(公告)日：1990-03-06

申请号：JP21684488

申请日：1988-08-31

Applicant: TOSHIBA CORP ,  NIPPON TELEGRAPH & TELEPHONE

Inventor： WATANABE TAICHI ,  KIJIMA TORU ,  TANAKA SHUICHI ,  TOKUNAGA SATORU

IPC: H04B7/08

Abstract: PURPOSE:To attain the transit from opposite phase to in-phase accurately in a short time by generating a phase control signal inverting the phase shift of the phase shifter by 180 deg. based on a phase control signal and supplying it to the phase shifter when the 1st and 2nd reception intermediate frequency signals are in opposite phase. CONSTITUTION:When the phase of a main reception intermediate frequency signal IM and the sub reception intermediate frequency signal IS enters in opposite state, a gain control voltage GS from a gain control circuit 52 is reduced as shown by figure 4 and the opposite phase state is detected by a Schmitt trigger circuit 54. A logic level of the most significant bit A7 of an up-down counter 11 is inverted by a phase inverting circuit 20 and the inverted phase control address JS is fed to an infinite phase shifter. The phase shift of the infinite phase shifter is inverted by 180 deg. momentarily accordingly and the phase of the sub reception intermediate frequency signal IS is shifted momentarily by 180 deg.. Thus, the transit from the opposite phase to the in-phase is implemented accurately in a short time regardless of simple constitution.

公开(公告)号：JPS6488982A

公开(公告)日：1989-04-03

申请号：JP24401987

申请日：1987-09-30

Applicant: TOSHIBA CORP

Inventor： TANAKA SHUICHI ,  KAKIZAKI MIKIO

IPC: G11B27/02 ,  G11B27/034

Abstract: PURPOSE:To store the code data of a selected block without being over a time limit which is previously set by deciding respective rest time from the respective total time of the set first and second time limit and the block preferentially selected to operate the new block of a time length being in conformity with the rest time. CONSTITUTION:A reproducing and editing device is applied to a CD device, the operation of a key switch 11 is decoded by a key switch decoding part 12, a CD reproducing part 14 is made to be a prescribed operated state by a sequence control part 13. This reproducing part 14 picks up 18 the data recorded on a disk 17, a signal processing part 20 processes the data and a servocontrol part 21 processes an error signal. A memory address control part 26, a block length calculating part 28, a local longest block selecting part 30, a rest time arithmetic part 31 and a comparison arithmetic part 29 are connected to a memory part 22 on which the output of the reproducing part 14 is recorded and respectively controlled by a block selection control part 27. Then, the rest blank part is reduced and the good reproduction is realized.

公开(公告)号：JPS61153890A

公开(公告)日：1986-07-12

申请号：JP27830284

申请日：1984-12-27

Applicant: TOSHIBA CORP ,  TOSHIBA AUDIO VIDEO ENG

Inventor： TANAKA SHUICHI ,  KANESHIGE TOSHIHIKO

IPC: G11B27/10

Abstract: PURPOSE:To detect the tape position by a rotary head at a track unit at a high speed by making a track address into plural separating codes, dividing one track into plural blocks and adding an address to respective codes and blocks. CONSTITUTION:One track is divided to a constant number (k) of blocks, to respective blocks BL1,... a synchronizing signal SYN, a block address BA, separating bit DBA and data D are added respectively, the rotating position information of the head is formed 16, after modulation, recorded through a head 31 to a tape 40. Respective separating bits of a present position address and a desired position address 27 are compared in the order from the higher rank, a search speed corresponding to the order, in which first, the bits are dissident, is set 38, the coincidence and dissidence of a separating bit of one rank below the order, in which the bits are dissident during the search, are compared, at the time of the coincidence the search speed is held, at the time of dissidence the search speed is lowered by one rank, and further, the comparison of the separating bit of the order of one rank below is started. Thus, the purpose of the search can be achieved.

公开(公告)号：JP2011134410A

公开(公告)日：2011-07-07

申请号：JP2009294253

申请日：2009-12-25

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： TANAKA SHUICHI

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/06

CPC classification number: G11C29/785 ,  G11C29/28 ,  G11C2029/2602 ,  G11C2029/4402

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of shortening the test period, and to provide a test method of the same.
SOLUTION: The nonvolatile semiconductor memory device is equipped with: first and second memory cell arrays; flag registers which are prepared corresponding to respective blocks and capable of writing flag data by selecting block address; a control circuit for reading out the flag data of the first memory cell array and second memory cell array by arranging them in parallel; a first counter register for holding counted results of the flag data in the first memory cell array; and a second counter register for holding counted results of the flag data in the second memory cell array.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供能够缩短测试周期的非易失性半导体存储器件，并提供其测试方法。 解决方案：非易失性半导体存储器件配备有：第一和第二存储单元阵列; 标志寄存器，其对应于各个块准备并且能够通过选择块地址来写入标志数据; 控制电路，用于通过并行布置来读出第一存储单元阵列和第二存储单元阵列的标志数据; 第一计数器寄存器，用于保持第一存储单元阵列中的标志数据的计数结果; 以及第二计数器寄存器，用于保持第二存储单元阵列中的标志数据的计数结果。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2008172466A

公开(公告)日：2008-07-24

申请号：JP2007002953

申请日：2007-01-11

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： MURAKAMI YASUSHI ,  TANAKA SHUICHI

IPC: H04B7/15 ,  H04B7/08 ,  H04B7/10 ,  H04J1/00 ,  H04J11/00

Abstract: PROBLEM TO BE SOLVED: To provide a broadcast-wave repeating device capable of effectively removing the same-channel interference waves mixed into the signal zone of the synthetic signal of broadcast waves even in the case of the indistinct size of interference waves and direction and angle of the arrival of interference waves.
SOLUTION: In the broadcast-wave repeating device, a plurality of systems of OFDM signals received by array antennas 1-1 to 1-N are synthesized so that the received power is maximized by a synthetic section 3. In the broadcast-wave repeating installation, an interference-wave component contained in the synthetic output is offset with replica interference waves obtained by passing the interference-wave signal of an interference-wave synthetic section 4 through an FIR 6, and only desired waves are transmitted from a transmission section 10. The control of the filter factor of the FIR 6 and the on-off control of an output to the transmission section 10 are conducted by evaluating the magnitude of the output signal of a subtraction section 5 and the desired wave component of the output signal and the interference-wave component by a receiving-state decision section 7.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：即使在干扰波的大小不清楚的情况下，也能够提供能够有效地去除混合到广播波的合成信号的信号区域中的同一信道干扰波的广播波重复装置，以及 干扰波到达的方向和角度。 解决方案：在广播波重复装置中，由阵列天线1-1至1-N接收的多个OFDM信号系统被合成，使得接收功率由合成部分3最大化。在广播 - 波形重复安装时，包含在合成输出中的干扰波分量由通过FIR 6通过干扰波合成部分4的干扰波信号而获得的复制干扰波偏移，并且只有所需的波从传输 通过评估减法部分5的输出信号的大小和输出的期望波分量来进行对FIR 6的滤波器因子的控制和对发送部分10的输出的开关控制 信号和接收状态决定部分7的干扰波分量。（C）版权所有（C）2008，JPO＆INPIT