公开(公告)号：JP2005354464A

公开(公告)日：2005-12-22

申请号：JP2004173862

申请日：2004-06-11

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： FUJII YASUYUKI ,  NAKAYAMA SATORU

IPC: H04B7/15

Abstract: PROBLEM TO BE SOLVED: To realize a digital radio communication system and a communication control method thereof, with which a delay time difference doesn't occur in a transmission electric wave regardless of switching from a current transmitter to a standby transmitter by easily measuring a delay time difference between modulation waves of respective transmission waves between the current transmitter and the standby transmitter.
SOLUTION: Transmission waves from two transmitters 1A and 1B are measured by using a phase comparator pd to synchronize phases of two transmission waves, and pulse-like noise occurring in a phase difference error signal between transmission waves measured by the phase comparator pd is detected in the case of the presence of a delay time difference between modulation waves included in transmission waves from two transmitters 1A and 1B, and the delay time difference between modulation waves is minimized by adjusting a variable delay line 1d so as to minimize the pulse-like noise.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了实现数字无线电通信系统及其通信控制方法，无论从当前发射机到备用发射机的切换容易，在发射电波中不发生延迟时间差 测量当前发射机和备用发射机之间各个传输波的调制波之间的延迟时间差。 解决方案：通过使用相位比较器pd来测量来自两个发射器1A和1B的传输波，以同步两个传输波的相位，以及在由相位比较器pd测量的传输波之间的相位差误差信号中出现的脉冲状噪声 在来自两个发射机1A和1B的传输波中包括的调制波之间存在延迟时间差的情况下检测到，并且通过调节可变延迟线1d使调制波之间的延迟时间差最小化，以使脉冲最小化 像噪音。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JPH06261023A

公开(公告)日：1994-09-16

申请号：JP4656293

申请日：1993-03-08

Applicant: TOSHIBA CORP ,  TOSHIBA AVE KK

Inventor： TANAKA SHUICHI ,  FUJII YASUYUKI ,  UMEKI MASAHIKO

IPC: G06F11/10 ,  H04J3/06 ,  H04L1/00 ,  H04L7/00

Abstract: PURPOSE:To enhance a data transmission efficiency by implementing multi-frame synchronization and interleave frame synchronization based on common synchronization information thereby reducing the number of synchronization information sets. CONSTITUTION:Frame synchronization word insertion circuits 21-I, 21-Q insert one FEC synchronization word per one FEC frame to each of I and Q series digital signals respectively and constitute one multi-frame with 5 FEC frames and multi-frame synchronization information is added to the FEC synchronization word inserted to the head FEC frame. First memories 24-I, 24-Q and 2nd memories 25-I, 25-Q are subjected to frame processing and code logic arithmetic operation circuits 23-I, 23-Q interleave each of I and Q series digital signals for each of the 5 FEC frames being one multi-frame.

公开(公告)号：JPH0661976A

公开(公告)日：1994-03-04

申请号：JP21261092

申请日：1992-08-10

Applicant: TOSHIBA CORP ,  TOSHIBA AVE KK

Inventor： TANAKA SHUICHI ,  FUJII YASUYUKI ,  UMEKI MASAHIKO

IPC: H03M13/00 ,  H04L1/00

Abstract: PURPOSE:To individually attain a function test, and to easily specify an abnormality generating part. CONSTITUTION:A delay circuit 26 branch-inputs data inputted to an encoding arithmetic logic circuit 24, and delays the data in a prescribed time. A selector 33 supplies encoded data error correction-encoded by the encoding arithmetic logic circuit 24 to a decoding arithmetic logic circuit 35 as necessary. A redundant bit selecting circuit 37 selects the data outputted from the delay circuit 26 in a period in which the inputted decoded data are a redundant bit part according to a switching signal from a timing generating circuit 36.

公开(公告)号：JPH04207809A

公开(公告)日：1992-07-29

申请号：JP34035190

申请日：1990-11-30

Applicant: TOSHIBA CORP

Inventor： FUJII YASUYUKI ,  TANAKA SHUICHI

IPC: H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H04B3/04 ,  H04B3/23 ,  H04L25/03

Abstract: PURPOSE:To shorten the integrating time and to improve the control responsiveness against the increase of the inter-code interference value by selecting the output equivalent to the prescribed number of bits of the upper or lower stage of a counter through a selector means in accordance with the inter-code interference value and using the selected output for control of the weighting value of a weighting means. CONSTITUTION:The correlation detection output o f a correlation detector 301 is applied to an up-down counter 402. Thus the counter 402 is counted up or down. Then the count output equivalent to 8 bits is selected in response to the selection signals a1, a2, a3... equivalent to the inter-code value. If the inter-code inference value is increased with occurrence of the distortion of transmission like the fading, etc., 8 bits are selected at the lower stage side of the count output. Meanwhile 8 bits are selected at the upper stage side of the count output are selected and a long integrating time is set if no fading occurs and a transmission line has a stable state.

公开(公告)号：JPH03135140A

公开(公告)日：1991-06-10

申请号：JP27180389

申请日：1989-10-20

Applicant: TOSHIBA CORP

Inventor： TANAKA SHUICHI ,  FUJII YASUYUKI

IPC: H04L27/00 ,  H04L27/36

Abstract: PURPOSE:To improve the detection capability by generating a signal interruption detection signal when either of an output of a means discriminating the presence of a base band signal and an output of a means of AND processing of its inputs is consecutively missing for a prescribed time or over. CONSTITUTION:Suppose that all of binary digital signals S11 - S22 or a clock signal CLK is missing or all of the signals S11,S21 of S12,S22 is missing, then base band signal outputs IS,QS of D/A converters 12I,12Q are both missing or either of them is missing. Thus, a discrimination output of comparators 21I,21Q of a signal interrupt detection circuit 20 goes to an L level. Then an L level signal, i.e., an alarm signal is generated after laps of a prescribed time from the generation of input interruption from either or both of one-shot multivibrators 22I,22Q is generated and the alarm signal is outputted via an AND circuit 23. Thus, input interruption of the binary digital signals S11 - S22 is detected without missing of detection.

公开(公告)号：JP2012195888A

公开(公告)日：2012-10-11

申请号：JP2011059921

申请日：2011-03-17

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： UJIIE TATSUNORI ,  FUJII YASUYUKI

IPC: H04B1/04 ,  H04J3/00

Abstract: PROBLEM TO BE SOLVED: To provide a digital wireless microwave transmission device in a small size and with high operational stability.SOLUTION: According to an embodiment, a digital wireless microwave transmission device comprises an interface module, an analog-to-digital conversion module, an FM modulation module, a digital modulation module, and a transmission module. The interface module captures a digital main signal and an analog auxiliary signal. The analog-to-digital conversion module digitizes the auxiliary signal. The FM modulation module generates a modulation signal by performing frequency modulation (FM) on the main signal based on the digitized auxiliary signal in a digital region. The digital modulation module generates a transmission signal by performing digital modulation on the modulation signal. The transmission module transmits the transmission signal wirelessly.

Abstract translation: 要解决的问题：提供一种小尺寸，高操作稳定性的数字无线微波传输装置。 解决方案：根据实施例，数字无线微波传输设备包括接口模块，模数转换模块，FM调制模块，数字调制模块和传输模块。 接口模块捕获数字主信号和模拟辅助信号。 模数转换模块将辅助信号数字化。 FM调制模块通过在数字区域中基于数字化的辅助信号对主信号进行调频（FM）来产生调制信号。 数字调制模块通过对调制信号进行数字调制来生成发送信号。 传输模块无线传输传输信号。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2009049663A

公开(公告)日：2009-03-05

申请号：JP2007213155

申请日：2007-08-17

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： FUJII YASUYUKI

IPC: H04B7/08

Abstract: PROBLEM TO BE SOLVED: To provide a receiver and a reception processing method, capable of adjusting a delay time difference of a received signal to easily perform SD multiplexing.
SOLUTION: A phase comparator 4 is used to measure an IF signal of a received wave of each system for performing diversity reception to arrange a phase of carrier waves, when a delay time difference exists between respective envelopes included in two IF signals, pulse-shaped noise that occurs in a phase difference error signal between the envelopes of respective IF signals measured by the phase comparator 4 is detected, and a variable delay line 5b is adjusted so as to minimize the pulse-shaped noise to thereby minimize the delay time difference between the envelopes of each received signal.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够调整接收信号的延迟时间差以容易地执行SD复用的接收机和接收处理方法。 解决方案：当在两个IF信号中包括的各个信封之间存在延迟时间差时，相位比较器4用于测量每个系统的接收波的IF信号，用于执行分集接收以布置载波的相位， 检测在由相位比较器4测量的各个IF信号的包络之间的相位差误差信号中发生的脉冲形噪声，并且调节可变延迟线5b以使脉冲形噪声最小化，从而使延迟最小化 每个接收信号的信封之间的时间差。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JPH05327646A

公开(公告)日：1993-12-10

申请号：JP12895392

申请日：1992-05-21

Applicant: TOSHIBA CORP

Inventor： FUJII YASUYUKI ,  TANAKA SHUICHI

IPC: H04J3/06 ,  H04L7/08

Abstract: PURPOSE:To change the frame synchronization state into an asynchronization state by discriminating the presence of detection of a frame bit pattern in one frame so as to surely detect out of frame synchronism. CONSTITUTION:A decoder 10 takes into account information representing final frame bit location of a frame outputted from frame counters 4, 5 without fail and only when a last frame bit is detected at the final frame bit position, it is discriminated that a frame bit pattern of one frame is correctly detected. Even when a correct frame bit is not detected in a sub frame on its way as the case that out of frame synchronism takes place with sub frame synchronization taken for example, it is prevented that it is immediately discriminated in the frame synchronization state when a bit coincident with a last frame bit is detected at the final frame bit location and out of frame synchronism is surely checked.

公开(公告)号：JPH05199270A

公开(公告)日：1993-08-06

申请号：JP1000792

申请日：1992-01-23

Applicant: TOSHIBA CORP ,  NIPPON TELEGRAPH & TELEPHONE

Inventor： TANAKA SHUICHI ,  FUJII YASUYUKI ,  HOSHINO HIROBUMI

IPC: H04L27/34 ,  H04L27/22

Abstract: PURPOSE:To prevent the out of synchronism and to attain smooth changeover by using also an output of a demodulation circuit of the delay detection system just after a standby system is selected and selecting an output of a demodulation circuit of the synchronization detection system in the stage when the synchronization is estab lished CONSTITUTION:When a receiver 400b of a standby system is started, a demodulation circuit 9' of the synchronization detection system and a demodulation circuit 9'' of the delay detection system are respectively operated. A control circuit 20 controls the equipment to select an output of the demodulation circuit 9'' just after the standby system is selected and switches a changeover switch 11' to the position of the demodulation circuit 9' in the stage that the synchronization is established. Then a demodulation output of the demodulation circuit 9' is given to processing circuits after an error correction circuit decoder 10'. Thus, no out of synchronism takes place even in the presence of a momentary interruption or frequency deviation or the like at transmitters 100a, 100b by employing delay detection in the initial stage of the switching of the receiver 400b of the standby system and the receiver 400a of the active system and then the changeover of the receivers 400a, 400b is smoothly implemented.

公开(公告)号：JPH04372247A

公开(公告)日：1992-12-25

申请号：JP15018791

申请日：1991-06-21

Applicant: TOSHIBA CORP

Inventor： FUJII YASUYUKI ,  TANAKA SHUICHI

IPC: H04L1/00 ,  H04L27/00 ,  H04L27/18

Abstract: PURPOSE:To reduce the cost of a speed conversion circuit and to allow the MODEM to cope with even a fast signal speed of each channel sufficiently. CONSTITUTION:A device in which a 1st speed conversion means 103 adds a space for error correction code to a transmission signal, adds an error correction code to the result, modulates it and the modulated signal is transmitted. A reception signal is demodulated and processed based on the error correction code at an error correction processing means, the space for correction code is eliminated and the result is decoded into the original transmission signal, is provided with a 1st distribution means 102 distributing the transmission signal into plural series before the 1st speed conversion means, with a 1st series conversion means 106 restoring the plural series of the signals with an error correction code added thereto to the series before the distribution to form the modulation system. The demodulation system is provided with a 2nd distribution means distributing the demodulated reception signal into plural series and giving the result to an error correction processing means, a 2nd speed conversion means eliminating the space for the correction code from the signal after error correction processing and with a 2nd series conversion means restoring the plural series of signals after space is eliminated into the series before the distribution.