公开(公告)号：US20170178972A1

公开(公告)日：2017-06-22

申请号：US15447126

申请日：2017-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

公开(公告)号：US09627268B2

公开(公告)日：2017-04-18

申请号：US14884746

申请日：2015-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

公开(公告)号：US09502519B2

公开(公告)日：2016-11-22

申请号：US14636125

申请日：2015-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L21/336 ,  H01L29/792 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7827

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a second dielectric layer thereon; forming a drain layer in the first dielectric layer and the second dielectric layer; forming a gate layer on the second dielectric layer; forming a channel layer in the gate layer; forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer; and forming a source layer in the third dielectric layer and the fourth dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有第一介电层和第二介电层的基板; 在所述第一电介质层和所述第二电介质层中形成漏极层; 在所述第二电介质层上形成栅极层; 在栅极层中形成沟道层; 在栅极层和沟道层上形成第三电介质层和第四电介质层; 以及在所述第三电介质层和所述第四电介质层中形成源极层。

公开(公告)号：US20160233303A1

公开(公告)日：2016-08-11

申请号：US14640033

申请日：2015-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Huai-Tzu Chiang

IPC: H01L29/10 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure with nanowire structures. The semiconductor structure includes a substrate, more than one first source/drain disposed on the substrate, and at least one first nanowire structure disposed on the first source/drain, wherein each first source/drain and the first nanowire structure are on different levels.

Abstract translation: 本发明提供一种具有纳米线结构的半导体结构。 半导体结构包括衬底，设置在衬底上的多于一个的第一源极/漏极，以及设置在第一源极/漏极上的至少一个第一纳米线结构，其中每个第一源极/漏极和第一纳米线结构处于不同的电平。

公开(公告)号：US20160211368A1

公开(公告)日：2016-07-21

申请号：US14636125

申请日：2015-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/42392 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7827

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a second dielectric layer thereon; forming a drain layer in the first dielectric layer and the second dielectric layer; forming a gate layer on the second dielectric layer; forming a channel layer in the gate layer; forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer; and forming a source layer in the third dielectric layer and the fourth dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有第一介电层和第二介电层的基板; 在所述第一电介质层和所述第二电介质层中形成漏极层; 在所述第二电介质层上形成栅极层; 在栅极层中形成沟道层; 在栅极层和沟道层上形成第三电介质层和第四电介质层; 以及在所述第三电介质层和所述第四电介质层中形成源极层。

公开(公告)号：US20150072272A1

公开(公告)日：2015-03-12

申请号：US14023476

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Hsin-Yu Chen ,  Kai-Lin Chuang

IPC: G03F1/72 ,  G03F1/00

CPC classification number: G03F1/72 ,  G03F1/144 ,  G03F1/36

Abstract: A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method.

Abstract translation: 提供一种形成光掩模的方法。 提供与第一行相关的第一照片掩模图案，与第一通孔插头相关的原始第二照片掩模图案和与第二行相关的第三照片掩模图案。 执行第一光学邻近校正（OPC）处理。 执行第二OPC处理，包括沿着第一方向放大第二光掩模图案的宽度以形成修改的第二光刻胶图案。 执行轮廓模拟处理以确保修改的第二光掩模图案大于或等于原始第二掩模图案。 输出第一光掩模图案，修改的第二光掩模图案和第三光掩模图案。 本发明还提供一种OPC方法。

公开(公告)号：US20140220482A1

公开(公告)日：2014-08-07

申请号：US14259173

申请日：2014-04-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Chia-Wei Huang ,  Chun-Hsien Huang ,  Shih-Chun Tsai ,  Kai-Lin Chuang

IPC: G03F1/36

CPC classification number: G03F1/36 ,  G03F1/00 ,  G03F1/68 ,  G03F1/70

Abstract: A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer.

Abstract translation: 形成图案的方法包括以下步骤。 提供了包括第一目标图案和第一不可打印虚设图案的第一布局。 提供包括第二目标图案和第二可打印虚拟图案的第二布局，其中第二可打印虚拟图案的至少一部分与第一不可打印虚设图案曝光极限重叠，使得第二可打印虚设图案不能形成在晶片中。

公开(公告)号：US08748066B2

公开(公告)日：2014-06-10

申请号：US13633876

申请日：2012-10-03

Applicant: United Microelectronics Corp.

Inventor： Hsin-Yu Chen ,  Chia-Wei Huang ,  Chun-Hsien Huang ,  Shih-Chun Tsai ,  Kai-Lin Chuang

IPC: G03F9/00

CPC classification number: G03F1/36 ,  G03F1/00 ,  G03F1/68 ,  G03F1/70

Abstract: A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer.

Abstract translation: 一种形成光掩模的方法包括以下步骤。 提供了包括第一目标图案和第一不可打印虚设图案的第一光掩模。 提供了包括第二目标图案和第二可打印虚设图案的第二光掩模，其中第二可打印虚拟图案的至少一部分与第一不可打印虚设图案曝光极限重叠，使得第二可打印虚拟图案不能被印刷在晶片 。

公开(公告)号：US20140093814A1

公开(公告)日：2014-04-03

申请号：US13633876

申请日：2012-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Chia-Wei Huang ,  Chun-Hsien Huang ,  Shih-Chun Tsai ,  Kai-Lin Chuang

IPC: G03F1/68

CPC classification number: G03F1/36 ,  G03F1/00 ,  G03F1/68 ,  G03F1/70

Abstract: A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer.

Abstract translation: 一种形成光掩模的方法包括以下步骤。 提供了包括第一目标图案和第一不可打印虚设图案的第一光掩模。 提供了包括第二目标图案和第二可打印虚设图案的第二光掩模，其中第二可打印虚拟图案的至少一部分与第一不可打印虚设图案曝光极限重叠，使得第二可打印虚拟图案不能被印刷在晶片 。

公开(公告)号：US20130299949A1

公开(公告)日：2013-11-14

申请号：US13947125

申请日：2013-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsiung Huang ,  Chun-Mao Chiou ,  Hsin-Yu Chen ,  Yu-Han Tsai ,  Ching-Li Yang ,  Home-Been Cheng

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L2224/13 ,  H01L2924/1461 ,  H01L2924/00

Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.

Abstract translation: 本发明涉及一种硅通孔（TSV）。 TSV设置在包括穿过基板的第一表面和第二表面的通孔的基板中。 TSV包括绝缘层，阻挡层，缓冲层和导电电极。 绝缘层设置在通孔开口的表面上。 阻挡层设置在绝缘层的表面上。 缓冲层设置在阻挡层的表面上。 导电电极设置在缓冲层的表面上，通孔开口的其余部分被导电电极完全填充。 缓冲层的一部分还在第二表面的一侧覆盖导电电极的表面，并且所述部分与第二表面平齐。