公开(公告)号：US20230129579A1

公开(公告)日：2023-04-27

申请号：US17528159

申请日：2021-11-16

Applicant: United Microelectronics Corp.

Inventor： Hao-Ming Lee ,  Ta Kang Lo ,  Tsai-Fu Chen ,  Shou-Wei Hsieh

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

Abstract: A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.

公开(公告)号：US10439023B2

公开(公告)日：2019-10-08

申请号：US16040319

申请日：2018-07-19

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/225 ,  H01L21/768

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US09666687B1

公开(公告)日：2017-05-30

申请号：US15187795

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Ming Lee ,  Sheng-Hao Lin ,  Huai-Tzu Chiang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L29/66666 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7827

Abstract: The present invention provides a method for forming a semiconductor structure, at least including the following steps: first, four sacrificial patterns are formed on a substrate, and a plurality of spacers are then formed surrounding each sacrificial pattern. Next, the four sacrificial patterns are removed, and a photoresist layer is formed between each spacer, covering parts of each spacer. Afterwards, a first etching process is performed to partially remove each spacer, and the photoresist layer is then removed, and a second etching process is then performed, to remove each spacer again, and to form four nanowire hard masks.

公开(公告)号：US20170104070A1

公开(公告)日：2017-04-13

申请号：US14940867

申请日：2015-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US09281400B1

公开(公告)日：2016-03-08

申请号：US14726620

申请日：2015-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Hao-Ming Lee ,  Tzyy-Ming Cheng

IPC: H01L21/339 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/8258

Abstract: A method of fabricating a semiconductor device with fin-shaped structures includes respectively forming first fin-shaped structures in a first region and a second region of a semiconductor substrate, depositing a dielectric layer to completely cover the first fin-shaped structures, removing the first fin-shaped structures in the second region so as to form trenches in the dielectric layer, and performing an in-situ doping epitaxial growth process so as to respectively form second fin-shaped structures in the trenches.

Abstract translation: 制造具有鳍状结构的半导体器件的方法包括分别在半导体衬底的第一区域和第二区域中形成第一鳍状结构，沉积介电层以完全覆盖第一鳍状结构，去除第一 在第二区域中形成鳍状结构，以便在电介质层中形成沟槽，并且进行原位掺杂外延生长工艺以在沟槽中分别形成第二鳍状结构。

公开(公告)号：US10211311B2

公开(公告)日：2019-02-19

申请号：US15984426

申请日：2018-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Ming Lee ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.

公开(公告)号：US10177231B2

公开(公告)日：2019-01-08

申请号：US15797011

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L29/165 ,  H01L21/3065

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20180102411A1

公开(公告)日：2018-04-12

申请号：US15834082

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

公开(公告)号：US09837493B2

公开(公告)日：2017-12-05

申请号：US14940867

申请日：2015-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20160336401A1

公开(公告)日：2016-11-17

申请号：US15221617

申请日：2016-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L21/324 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3247 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

Abstract translation: 本发明提供了在一个基底上形成具有不同直径的至少两种不同纳米线结构的一些方法。 由于纳米线结构的直径将影响纳米线场效应晶体管的阈值电压（Vt）和驱动电流，所以在本发明中，可以在一个衬底上形成具有不同直径的至少两个纳米线结构。 因此，在以下步骤中，这些纳米线结构可以应用于具有不同Vt和驱动电流的不同纳米线场效应晶体管中。 这样，可以提高纳米线场效应晶体管的灵活性。