公开(公告)号：US08779513B2

公开(公告)日：2014-07-15

申请号：US13869037

申请日：2013-04-24

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

Abstract translation: 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。

公开(公告)号：US11165019B2

公开(公告)日：2021-11-02

申请号：US16576784

申请日：2019-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Kuo-Chih Lai ,  Wei-Ming Hsiao ,  Hui-Ting Lin ,  Szu-Yao Yu ,  Nien-Ting Ho ,  Hsin-Fu Huang ,  Chin-Fu Lin

IPC: H01L45/00

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

公开(公告)号：US11133418B2

公开(公告)日：2021-09-28

申请号：US16413425

申请日：2019-05-15

Applicant: United Microelectronics Corp.

Inventor： Yen-Chen Chen ,  Xiao Wu ,  Hai Tao Liu ,  Ming Hua Du ,  Shouguo Zhang ,  Yao-Hung Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

公开(公告)号：US11011376B2

公开(公告)日：2021-05-18

申请号：US16242994

申请日：2019-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

IPC: H01L21/76 ,  H01L21/02 ,  H01L29/20 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and an above-surface portion formed on the blocking layer.

公开(公告)号：US20210143212A1

公开(公告)日：2021-05-13

申请号：US17157952

申请日：2021-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01F41/34 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

公开(公告)号：US10381228B2

公开(公告)日：2019-08-13

申请号：US14631807

申请日：2015-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chih-Chien Liu ,  Hsin-Kuo Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

公开(公告)号：US10290710B2

公开(公告)日：2019-05-14

申请号：US15696167

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Ming-Chang Lu ,  Wei Chen ,  Hui-Lin Wang ,  Yi-Ting Liao ,  Chin-Fu Lin

IPC: H01L29/10 ,  H01L21/385 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

公开(公告)号：US20190074357A1

公开(公告)日：2019-03-07

申请号：US15696167

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Ming-Chang Lu ,  Wei Chen ,  Hui-Lin Wang ,  Yi-Ting Liao ,  Chin-Fu Lin

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/51 ,  H01L21/385 ,  H01L29/66

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

公开(公告)号：US09401429B2

公开(公告)日：2016-07-26

申请号：US13917623

申请日：2013-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a suspended part. The gate surrounds the suspended part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a suspended part in the corresponding top part, thereby forming the suspended part over a through hole. A gate is formed to surround the suspended part.

Abstract translation: 半导体结构包括鳍状结构和栅极。 鳍状结构位于基板中，其中鳍状结构具有位于悬挂部分正下方的通孔。 门围绕悬挂部分。 此外，本发明还提供一种半导体工艺，包括用于形成所述半导体结构的以下步骤。 提供基板。 在基板上形成翅片状结构，其中，翅片状结构具有底部和顶部。 底部的一部分被去除以在相应的顶部部分中形成悬挂部分，从而在悬空部分上形成通孔。 形成围绕悬挂部分的门。

公开(公告)号：US20160211144A1

公开(公告)日：2016-07-21

申请号：US14631807

申请日：2015-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chih-Chien Liu ,  Hsin-Kuo Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3065

CPC classification number: H01L21/30608 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785

Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

Abstract translation: 施加光照射的外延工艺包括以下步骤。 提供基板。 执行干蚀刻工艺和湿蚀刻工艺以在衬底中形成凹部，其中在执行湿蚀刻工艺时红外光照亮。 在凹部中形成外延结构。