公开(公告)号：JP2003264435A

公开(公告)日：2003-09-19

申请号：JP2002061107

申请日：2002-03-06

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN ,  NORO MASAO

IPC: H03F3/217

Abstract: PROBLEM TO BE SOLVED: To provide a D-class amplifier capable of driving and controlling power MOS (metal oxide semiconductor) transistors for output without using a particular circuit technology and electronic components. SOLUTION: A signal generation circuit 301H generates and outputs a common mode signal H1 and an opposite phase signal H2 of a modulated pulse signal. A signal conversion circuit 302H converts the common mode signal H1 and the opposite phase signal H2 into a common mode signal H3 and an opposite phase signal H4 following the voltage VR1 making source voltage VS of the MOS transistor 401 for output a reference while maintaining size relation between a signal level of the common-mode signal H1 and a signal level of the opposite phase signal H2. Then, a driving circuit 303H is activated by an internal power source P12 making the source voltage VS a reference and drives the MOS transistor 401 for output based on the size relation between the common-mode signal H3 and the opposite phase signal H4. Similarly, a MOS transistor 402 for output is complementarily driven for the MOS transistor 401. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2000012704A

公开(公告)日：2000-01-14

申请号：JP17776398

申请日：1998-06-24

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C11/405 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To prevent the leakage of the electric charges corresponding to data due to interference caused by random access, etc. SOLUTION: In a semiconductor memory cell in which electric charges are stored corresponding to the levels of write bit lines WBit under instructions from write word lines WWrd and, meanwhile, the levels of readout bit lines RBit are made to transit under instructions from readout work lines RWrd, the write word lines WWrd are laid between grounding lines GND and the readout word lines RWrd.

公开(公告)号：JPH08180695A

公开(公告)日：1996-07-12

申请号：JP33826894

申请日：1994-12-27

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C17/00 ,  G11C11/41 ,  G11C16/06

Abstract: PURPOSE: To increase the speed of access in a NAND type mask ROM by precharging the word line of the next address based on the result of judgement about the difference between the address data of consecutive timing. CONSTITUTION: External address data is alternately taken into two systems of address registers of an address buffer 2 by clocks CKA, CKB and sorted to be sent to a column decoder 4 and a row decoder 3 respectively where data is successively read. When the next address judging circuit 10 judges that the present address data AD is different from the next address data NAD, it sends a precharge enable signal to the column and row decoders for precharge 11, 14 to select and precharge only the bit line and word line of the next address. Thus, the precharge of unnecessary lines is eliminated to reduce power consumption and to enable fast access.

公开(公告)号：JPH0634676A

公开(公告)日：1994-02-10

申请号：JP19253292

申请日：1992-07-20

Applicant: YAMAHA CORP

Inventor： SHICHIMIYA TAKATOMO ,  TANAKA TAISHIN

IPC: G01R19/165 ,  G05F1/56 ,  H02H3/24

Abstract: PURPOSE:To output a control signal so that an IC can perform an initial function regardless of a supply voltage by outputting a comparison result between a divided voltage of the supply voltage and a reference voltage as a control voltage. CONSTITUTION:When a supply voltage VDD of an IC is lower than a specific voltage and the output voltage of a node S2 of a voltage-division circuit 2 is lower than that of a node S3 of a reference voltage generation circuit 3, the gate voltage of an N-channel MOSFET 15 becomes smaller than that of an N-channel MOSFET 16 of a comparison circuit 1, thus causing the level of the output voltage of a node 51 to be high. On the other hand, when the voltage VDD is higher than a specific voltage and the output voltage of the node S2 is higher than that of the node S3, the level of the output voltage of the node S1 becomes high. Therefore, using the output signal of the node S1 as a control signal, an optimum circuit configuration for a used supply voltage can be formed by switching the configuration of the circuit on a semiconductor chip and the IC can be controlled so that it can perform an initial function fully regardless of the voltage VDD.