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    Method of forming a silicide interconnect over a silicon comprising substrate and method of forming a stack of refractory metal nitride over refractory metal silicide over silicon
    41.
    发明授权
    Method of forming a silicide interconnect over a silicon comprising substrate and method of forming a stack of refractory metal nitride over refractory metal silicide over silicon 有权
    在包含硅的衬底上形成硅化物互连的方法以及在难熔金属硅化物上形成难熔金属氮化物堆的方法

    公开(公告)号：US06524951B2

    公开(公告)日：2003-02-25

    申请号：US09259216

    申请日：1999-03-01

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L214763

    CPC classification number: H01L21/28518

    Abstract: The invention encompasses methods of forming silicide interconnects over silicon comprising substrates. In one implementation, a first layer comprising a metal and a non-metal impurity is formed over a region of a silicon comprising substrate where a silicide interconnection is desired. An elemental metal comprising second layer is formed over the first layer. The substrate is annealed to cause a reaction between at least the elemental metal of the second layer and silicon of the substrate region to form a silicide of the elemental metal of the second layer. In another considered aspect, a method of forming a silicide interconnect over a silicon comprising substrate includes providing a buffering layer to silicon diffusion between a refractory metal comprising layer and a silicon containing region of a substrate. The substrate is annealed under conditions effective to diffuse at least some of at least one of the refractory metal and the silicon through the buffering layer to form a silicide of the refractory metal, with the buffering layer during the annealing reducing silicon consumption from the region over that which would otherwise occur under the same annealing conditions were the buffering layer not present. The invention also encompasses a method of forming a stack of refractory metal nitride over refractory metal silicide over silicon includes providing a silicon comprising substrate.

    Abstract translation: 本发明包括在包含硅的衬底上形成硅化物互连的方法。 在一个实施方案中，在包含硅的衬底的需要硅化物互连的区域上形成包括金属和非金属杂质的第一层。 包含第二层的元素金属形成在第一层上。 将衬底退火以在至少第二层的元素金属和衬底区域的硅之间引起反应，以形成第二层的元素金属的硅化物。 在另一个考虑的方面中，在包含硅的衬底上形成硅化物互连的方法包括提供缓冲层以在包含难熔金属的层和衬底的含硅区域之间的硅扩散。 衬底在有效地通过缓冲层扩散难熔金属和硅中的至少一种的至少一些的条件下进行退火，以形成难熔金属的硅化物，退火期间的缓冲层减少了来自该区域的硅消耗 否则在相同退火条件下发生的缓冲层不存在。 本发明还包括在硅之上的难熔金属硅化物上形成难熔金属氮化物堆叠的方法，包括提供包含硅的衬底。

    Method of forming a conductive line and method of forming a local interconnect
    42.
    发明授权
    Method of forming a conductive line and method of forming a local interconnect 有权
    形成导线的方法和形成局部互连的方法

    公开(公告)号：US06211054B1

    公开(公告)日：2001-04-03

    申请号：US09323749

    申请日：1999-06-01

    Applicant: Li Li ,  Yongjun Jeff Hu

    Inventor： Li Li ,  Yongjun Jeff Hu

    IPC: H01L21335

    CPC classification number: H01L21/76889 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/76895 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention includes methods of forming conductive lines, such as local interconnects. In one implementation, a method of forming a conductive line includes depositing a first layer comprising polymer silicon on a substrate. A metal layer is deposited at least over some portion of the first layer. After depositing the metal layer, the substrate is exposed to annealing conditions effective to form a metal silicide over the at least some portion. The metal silicide is provided into a desired conductive line shape. In one implementation, a method of forming a conductive line includes depositing a first layer comprising polymer silicon or amorphous silicon on a substrate. Only a portion of the first layer is exposed to both oxygen and ultraviolet light effective to transform at least an outer part of the portion to oxidized silicon. After the exposing to both oxygen and ultraviolet light, a metal layer is deposited at least over some portion of the first layer which was not subjected to the effective exposing to the combination of oxygen and ultraviolet light. After depositing the metal layer, the substrate is exposed to annealing conditions effective to form a metal silicide over the at least some portion. After the annealing, metal is removed from the metal layer which has not been transformed to metal silicide substantially selective relative to metal which has been so transformed.

    Abstract translation: 本发明包括形成导线的方法，例如局部互连。 在一个实施方案中，形成导线的方法包括在衬底上沉积包含聚合物硅的第一层。 至少在第一层的某一部分上沉积金属层。 在沉积金属层之后，将衬底暴露于有效地在至少一些部分上形成金属硅化物的退火条件。 将金属硅化物设置成所需的导线形状。 在一个实施方案中，形成导线的方法包括在衬底上沉积包含聚合物硅或非晶硅的第一层。 只有第一层的一部分暴露于氧和紫外光，有效地将至少部分的外部部分转化为氧化的硅。 在暴露于氧和紫外光之后，金属层至少沉积在不经受有效暴露于氧和紫外光的组合的第一层的某一部分上。 在沉积金属层之后，将衬底暴露于有效地在至少一些部分上形成金属硅化物的退火条件。 在退火之后，相对于已经如此转变的金属，金属从金属层中去除，该金属层没有被转变成基本选择性的金属硅化物。

    Apparatuses and devices for absorbing electromagnetic radiation, and methods of forming the apparatuses and devices
    45.
    发明授权
    Apparatuses and devices for absorbing electromagnetic radiation, and methods of forming the apparatuses and devices 有权
    用于吸收电磁辐射的装置和装置，以及形成装置和装置的方法

    公开(公告)号：US08797662B2

    公开(公告)日：2014-08-05

    申请号：US12967733

    申请日：2010-12-14

    Applicant: Yongjun Jeff Hu ,  Allen McTeer ,  Lijing Gou

    Inventor： Yongjun Jeff Hu ,  Allen McTeer ,  Lijing Gou

    IPC: G02B5/22 ,  G02B5/20 ,  B82Y20/00

    CPC classification number: G02B5/201 ,  B82Y20/00 ,  G02B5/003 ,  Y10S977/707 ,  Y10S977/762 ,  Y10S977/773 ,  Y10S977/834 ,  Y10S977/954

    Abstract: Photonic nanostructures, light absorbing apparatuses, and devices are provided. The photonic nanostructures include a plurality of photonic nanobars configured to collectively absorb light over an excitation wavelength range. At least two of the photonic nanobars of the plurality have lengths that are different from one another. Each photonic nanobar of the plurality has a substantially small width and a substantially small height relative to the different lengths. A method for forming such may comprise forming a plurality of first photonic nanobars comprising a width and a height that are smaller than a length of the plurality of first photonic nanobars, and forming a plurality of second photonic nanobars comprising a width and a height that are smaller than a length of the second photonic nanobar, wherein the lengths of the plurality of first photonic nanobars and the lengths of the plurality of second photonic nanobars are different from one another.

    Abstract translation: 提供光子纳米结构，光吸收装置和装置。 光子纳米结构包括配置成在激发波长范围内共同吸收光的多个光子纳米结构。 多个光子纳米棒中的至少两个具有彼此不同的长度。 多个的每个光子纳米棒相对于不同的长度具有基本上小的宽度和基本上小的高度。 用于形成其的方法可以包括形成多个第一光子纳米条，其包括小于多个第一光子纳米条的长度的宽度和高度，以及形成多个第二光子纳米条，其包括宽度和高度 小于第二光子纳米棒的长度，其中多个第一光子纳米棒的长度和多个第二光子纳米棒的长度彼此不同。

    Methods of forming transistor gates
    46.
    发明授权
    Methods of forming transistor gates 有权
    形成晶体管栅极的方法

    公开(公告)号：US08716119B2

    公开(公告)日：2014-05-06

    申请号：US13605848

    申请日：2012-09-06

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

    CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/792

    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

    Abstract translation: 一些实施例包括形成电荷存储晶体管栅极和标准FET栅极的方法，其中公共处理用于制造不同类型栅极的至少一些部分。 可以形成FET和电荷存储晶体管栅极堆叠。 栅极堆叠可以各自包括栅极材料，绝缘材料和牺牲材料。 牺牲材料从FET中去除并对存储晶体管栅极堆叠进行充电。 FET栅极堆叠的绝缘材料被蚀刻通过。 导电材料形成在FET栅叠层上方和电荷存储晶体管栅堆上。 导电材料物理地接触FET栅极堆叠的栅极材料，并且通过残留在电荷存储晶体管栅极堆叠中的绝缘材料与电荷存储晶体管栅极堆叠的栅极材料分离。 一些实施例包括门结构。

    Methods of forming semiconductor devices having diffusion regions of reduced width
    47.
    发明授权
    Methods of forming semiconductor devices having diffusion regions of reduced width 有权
    形成具有减小宽度的扩散区域的半导体器件的方法

    公开(公告)号：US08709929B2

    公开(公告)日：2014-04-29

    申请号：US13604411

    申请日：2012-09-05

    Applicant: Lequn Liu ,  Yongjun Jeff Hu ,  Anish A. Khandekar

    Inventor： Lequn Liu ,  Yongjun Jeff Hu ,  Anish A. Khandekar

    IPC: H01L21/265 ,  H01L29/78

    CPC classification number: H01L21/2652 ,  H01L21/26513 ,  H01L27/11526 ,  H01L27/11548 ,  H01L29/6659 ,  H01L29/66659

    Abstract: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion regions in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width.

    Abstract translation: 提供了用于形成半导体器件的半导体器件和方法，包括在半导体中包括一个或多个扩散区域的半导体器件，所述一个或多个扩散区域与邻近半导体表面形成的栅极相邻（例如，半导体衬底 ）。 一个或多个扩散区域包括在半导体表面下方的深度处的第一宽度和靠近半导体表面的第二宽度，一个或多个扩散区域的第二宽度小于第一宽度的大约40％ 宽度。

    Capacitors including at least two portions of a metal nitride material, methods of forming such structures, and semiconductor devices including such structures
    49.
    发明授权
    Capacitors including at least two portions of a metal nitride material, methods of forming such structures, and semiconductor devices including such structures 有权
    包括金属氮化物材料的至少两部分的电容器，形成这种结构的方法以及包括这种结构的半导体器件

    公开(公告)号：US08564094B2

    公开(公告)日：2013-10-22

    申请号：US12556266

    申请日：2009-09-09

    Applicant: Yongjun Jeff Hu

    Inventor： Yongjun Jeff Hu

    IPC: H01L29/94

    CPC classification number: H01L29/945 ,  H01L21/743 ,  H01L21/76846 ,  H01L21/76847 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects.

    Abstract translation: 金属 - 绝缘体 - 金属电容器，其具有包括金属氮化物材料的至少两部分的底部电极。 金属氮化物材料的至少一部分包括与另一部分不同的材料。 还公开了包括金属氮化物材料的至少两部分的互连件，金属氮化物材料的至少一部分由与金属氮化物材料的另一部分不同的材料形成。 还公开了制造这种MIM电容器和互连的方法，以及包括这种MIM电容器和互连的半导体器件。

    Methods of forming doped regions in semiconductor substrates
    50.
    发明授权
    Methods of forming doped regions in semiconductor substrates 有权
    在半导体衬底中形成掺杂区的方法

    公开(公告)号：US08329567B2

    公开(公告)日：2012-12-11

    申请号：US12938845

    申请日：2010-11-03

    Applicant: Jennifer Lequn Liu ,  Shu Qin ,  Allen McTeer ,  Yongjun Jeff Hu

    Inventor： Jennifer Lequn Liu ,  Shu Qin ,  Allen McTeer ,  Yongjun Jeff Hu

    IPC: H01L21/26 ,  H01L21/42

    CPC classification number: H01L21/2236 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26526 ,  H01L29/66575

    Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

    Abstract translation: 一些实施例包括在半导体衬底中形成一个或多个掺杂区域的方法。 可以使用等离子体掺杂来形成第一掺杂剂到衬底内的第一深度。 然后可以用第二掺杂剂冲击第一掺杂剂以将第一掺杂剂敲入衬底内的第二深度。 在一些实施方案中，第一掺杂剂是p型（例如硼），第二掺杂剂是中性型（例如锗）。 在一些实施方案中，第二掺杂剂比第一掺杂剂重。

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