SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
    41.
    发明申请
    SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF 有权
    半导体布置及其形成

    公开(公告)号:US20150253283A1

    公开(公告)日:2015-09-10

    申请号:US14200148

    申请日:2014-03-07

    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an electro-wetting-on-dielectric (EWOD) device. The EWOD device includes a top portion over a bottom portion and a channel gap between the top portion and the bottom portion. The bottom portion includes a driving dielectric layer over a first electrode, a second electrode and a first separating portion of an ILD layer between the first electrode and a second electrode. The driving dielectric layer has a first thickness less than about 1,000 Å. An EWOD device with a driving dielectric layer having a first thickness less 1000 Å requires a lower applied voltage to alter a shape of a droplet within the device and has a longer operating life than an EWOD device that requires a higher applied voltage to alter the shape of the droplet.

    Abstract translation: 提供了半导体布置和形成方法。 半导体装置包括电润湿电介质(EWOD)装置。 EWOD装置包括在底部上的顶部和顶部和底部之间的通道间隙。 底部包括位于第一电极和第二电极之间的第一电极,第二电极和ILD层的第一分离部分之间的驱动电介质层。 驱动电介质层具有小于约的第一厚度。 具有第一厚度小于1000埃的驱动电介质层的EWOD器件需要较低的施加电压以改变器件内的液滴的形状,并且具有比需要较高施加电压以改变形状的EWOD器件更长的工作寿命 的液滴。

    Microelectromechanical device having a common ground plane layer and a set of contact teeth and method for making the same
    43.
    发明申请
    Microelectromechanical device having a common ground plane layer and a set of contact teeth and method for making the same 有权
    具有公共接地层和一组接触齿的微机电装置及其制造方法

    公开(公告)号:US20050184836A1

    公开(公告)日:2005-08-25

    申请号:US10994703

    申请日:2004-11-20

    Inventor: Chia-Shing Chou

    Abstract: The present invention relates to MEM switches. More specifically, the present invention relates to a system and method for making MEM switches having a common ground plane. One method for making MEM switches includes: patterning a common ground plane layer on a substrate; forming a dielectric layer on the common ground plane layer; depositing a DC electrode region through the dielectric layer to contact the common ground plane layer; and depositing a conducting layer on the DC electrode region so that regions of the conducting layer contact the DC electrode region, so that the common ground plane layer provides a common ground for the regions of the conducting layer

    Abstract translation: 本发明涉及MEM开关。 更具体地,本发明涉及一种用于制造具有公共接地层的MEM开关的系统和方法。 制造MEM开关的一种方法包括:在衬底上构图公共接地层; 在公共接地层上形成介电层; 通过所述电介质层沉积DC电极区域以接触所述公共接地层; 以及在所述DC电极区域上沉积导电层,使得所述导电层的区域与所述DC电极区域接触,使得所述公共接地层提供所述导电层的区域的公共接地

    Method for registering a deposited material with channel plate channels
    44.
    发明申请
    Method for registering a deposited material with channel plate channels 失效
    用通道板通道注入沉积材料的方法

    公开(公告)号:US20050032379A1

    公开(公告)日:2005-02-10

    申请号:US10941350

    申请日:2004-09-14

    Abstract: A method for depositing material on a channel plate such that the material is registered to one or more channels formed in the channel plate includes filling at least one of the channels with a resist that is not wetted by the material; depositing the material on at least a region of the channel plate that includes at least part of the resist, the material registering with at least one channel edge as a result of the material's abutment to the resist; and then removing the resist. The method may be used, in one embodiment, to apply an adhesive or gasket material that is used in assembling a switch.

    Abstract translation: 一种用于在通道板上沉积材料使得该材料与通道板中形成的一个或多个通道对准的方法包括用未被该材料润湿的抗蚀剂填充至少一个通道; 在包括至少部分抗蚀剂的通道板的至少一个区域上沉积材料,由于材料与抗蚀剂的邻接,材料与至少一个通道边缘配准; 然后除去抗蚀剂。 在一个实施例中,可以使用该方法来施加用于组装开关的粘合剂或垫圈材料。

    Method for producing co-planar surface structures
    45.
    发明授权
    Method for producing co-planar surface structures 有权
    共面表面结构的制造方法

    公开(公告)号:US06284560B1

    公开(公告)日:2001-09-04

    申请号:US09215973

    申请日:1998-12-18

    CPC classification number: B81C1/00611 B81C2201/0121

    Abstract: A method for producing co-planar surface areas is disclosed. At first a first layer with at least one recess is provided. Onto the first layer a second layer is deposited over the entire area of the first layer wherein the second layer has a thickness greater than the depth of the recess. The second layer is composed of material different to the material of the first layer. The next step removes the second layer completely beyond the area of at least one recess. The remaining portion of the second layer is removed until the second layer is coplanar with the first layer.

    Abstract translation: 公开了一种制造共平面表面积的方法。 首先提供具有至少一个凹部的第一层。 在第一层上,第二层沉积在第一层的整个区域上,其中第二层的厚度大于凹槽的深度。 第二层由与第一层材料不同的材料组成。 下一步骤将第二层完全超过至少一个凹部的区域。 去除第二层的剩余部分直到第二层与第一层共面。

    Method for producing metal lines on top of a non-flat mems topography
    46.
    发明公开
    Method for producing metal lines on top of a non-flat mems topography 审中-公开
    on hen ie ie ie ie ie ie ie ie ie ie ie ie ie ie ie ie

    公开(公告)号:EP2679537A1

    公开(公告)日:2014-01-01

    申请号:EP12173761.3

    申请日:2012-06-27

    Applicant: IMEC

    Abstract: The present disclosure is related to a method for producing one or more structural elements (3,4) on top of at least two components of a Micro-Electromechanical System (MEMS) device, wherein a gap (10) is present between two of said components, the method comprising:
    ● filling said gap with a planarizing material,
    ● producing said elements on top of said two components (1,2),

    wherein filling said gap (10) consists of performing subsequently:
    ● a first step, being a sputtering step or a combined sputtering/deposition step, thereby widening the entrance to said gap, and,
    ● a second step, being a conformal deposition step, thereby filling said gap with a planarizing material and producing a substantially flat layer (17) of said material on top of said components (1,2).

    Abstract translation: 本公开涉及一种用于在微机电系统(MEMS)装置的至少两个部件的顶部上产生一个或多个结构元件(3,4)的方法,其中在所述两个所述 所述方法包括: - 用平坦化材料填充所述间隙, - 在所述两个部件(1,2)的顶部产生所述元件,其中填充所述间隙(10)包括随后执行: - 第一步骤 ,作为溅射步骤或组合的溅射/沉积步骤,从而扩大所述间隙的入口,以及作为共形沉积步骤的第二步骤,由此用平坦化材料填充所述间隙并产生基本平坦的层( 所述材料在所述部件(1,2)的顶部上。

    Method of manufacturing nanostructure arrays
    47.
    发明公开
    Method of manufacturing nanostructure arrays 审中-公开
    Verfahren zur Herstellung einer Anordnung von Nanostrukturen

    公开(公告)号:EP1568657A2

    公开(公告)日:2005-08-31

    申请号:EP05251031.0

    申请日:2005-02-23

    Abstract: A method of disposing a plurality of isolated particles of a first material onto a substrate comprising the steps of:

    (a) depositing a first species onto the substrate;
    (b) anodizing the first species to produce a second species;
    (c) altering the surface of the second species so that at least one first region of the second species is of greater thickness than at least one second region of the second species;
    (d) depositing the first material onto the second species; and
    (e) levelling the surface of the first material and the second species.

    Abstract translation: 将多个分离的第一材料的分离颗粒设置在基材上的方法,包括以下步骤:(a)将第一种子沉积到所述基材上; (b)阳极氧化第一种以产生第二种; (c)改变第二物质的表面,使得第二物质的至少一个第一区域比第二物质的至少一个第二区域具有更大的厚度; (d)将第一材料沉积到第二种上; 和(e)使第一材料和第二物质的表面平整。

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