Abstract:
A RFPA (radio frequency power amplifier) circuit (150) which includes a RFPA (101), a supply voltage source (104), means (155) for applying to the RFPA a gain control bias voltage and a feedback control loop (156) for adjusting a voltage applied to the RFPA, the feedback control loop including a sampler (107) for sampling an output of the RFPA, a RF detector (109) for detecting a level of RF power sampled by the sampler, a comparator (115) for comparing an output signal from the RF detector with a reference signal, an integrator (117) for integrating an output signal of the comparator and a voltage regulator (151) having a first input from the integrator and a second input from the supply voltage source and an output connected to the RFPA, the regulator being operable to apply to the RFPA a supply voltage adjusted in response to an input signal from the integrator.
Abstract:
A RFPA (radio frequency power amplifier) circuit (150) which includes a RFPA (101), a supply voltage source (104), means (155) for applying to the RFPA a gain control bias voltage and a feedback control loop (156) for adjusting a voltage applied to the RFPA, the feedback control loop including a sampler (107) for sampling an output of the RFPA, a RF detector (109) for detecting a level of RF power sampled by the sampler, a comparator (115) for comparing an output signal from the RF detector with a reference signal, an integrator (117) for integrating an output signal of the comparator and a voltage regulator (151) having a first input from the integrator and a second input from the supply voltage source and an output connected to the RFPA, the regulator being operable to apply to the RFPA a supply voltage adjusted in response to an input signal from the integrator.
Abstract:
In a high frequency power amplifier circuit in which bias voltages are applied to the transistors for amplification by current mirroring, this invention enables preventing waveform distortion near the peak output power level by allowing sufficient idle currents to flow through the transistors for amplification, while enhancing the power efficiency in a low output power region. The power amplifier includes a detection circuit comprising a transistor for detection which receives the AC component of an input signal to the last-stage transistor for amplification at its control terminal, a current mirror circuit which mirrors current flowing through that transistor, and a current-voltage conversion means which converts current flowing in the slave side of the current mirror circuit into a voltage. In the detection circuit, a voltage from a bias circuit for generating the bias voltages for the transistors for amplification is applied to the control terminal of the transistor for detection and output of the detection circuit is applied to the control terminal of the last-stage transistor for amplification.
Abstract:
A dynamically varying linearity system nullDVLSnull capable of varying the linearity of a radio frequency (RF) front-end of a communication device responsive to receiving a condition signal indicating a desired mode of operation of a transmitter. The DVLS may include a condition signal indicative of the desired mode of operation and a controller that adjusts the linearity of the transmitter responsive to the condition signal. The condition signal may be responsive to a user interface. The controller, responsive to the condition signal, may dynamically adjust the operating current of the transmitter.
Abstract:
PROBLEM TO BE SOLVED: To enable preventing distortion of a waveform by applying a sufficient idle current to a transistor for amplification in the vicinity of the maximum level of an output power, and to enable improving power efficiency in a region where the output power is low, in a high-frequency power amplifier circuit for giving a bias to the transistor for amplification by a current mirror system. SOLUTION: A detection circuit (240) is provided which consists of a detection transistor (Q1) having a control terminal receiving the AC component of the input signal of the amplification transistor (213) of the final stage, current mirror circuits (Q2, Q3) for transferring a current flowing to the transistor, and a current-voltage converting means (Q4) for converting a current of the transfer side of the current mirror circuits into a voltage. A voltage from a bias circuit (230) for generating the bias voltage of the amplification transistor is applied to the control terminal of the detection transistor of the detection circuit, and the output of the detection circuit is applied to the control terminal of the amplification transistor of the final stage. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
본실시예는 DC 오프셋제거회로를개시한다. 본실시예에따른 DC 오프셋제거회로는 DCFB 대역(DC Feedback Bandwidth)을가변하는 DC 피드백부를구비하고, DC 드룹에러를저감하기위하여고대역에서중대역또는중대역에서저대역으로변환할때, 지연시간(Delay Time)을두어안정적으로 DC 오프셋을제거한다.
Abstract:
In a preferred embodiment, the gain expansion in low power mode of a single chain PA is minimized by dynamically adjusting the output impedance of the bias circuit of each gain stage for each mode of operation. Instead of switching in a series attenuator or switching in additional feedback in the first gain stage of a single-chain PA to limit the gain at the increased quiescent current level, this embodiment achieves linear performance by adjusting the quiescent current in each stage to the minimum level that meets the target gain and then increasing the output resistance of the bias circuit of each gain stage in low power mode (LPM) to provide the appropriate level of negative feedback at the base of each amplifying HBT to linearize the gain versus power response.
Abstract:
A device includes a variable gain amplifier, a voltage shifter, a variable gain amplifier half replica module, and an analog to digital converter. The variable gain amplifier includes an input terminal to receive an input signal, an output terminal to provide a first output signal that is biased based on a first common-mode voltage reference. The voltage shifter circuit includes first and second input terminals, and an output terminal to provide, to the analog to digital converter, a third output signal that is biased based on a second common-mode voltage reference. The variable gain amplifier half replica module includes an output terminal coupled to the second input terminal of the voltage shifter circuit, the variable gain amplifier half replica module to control the third output signal of the voltage shifter circuit based on the first common-mode voltage reference and the second common-mode voltage reference.
Abstract:
An audio apparatus is configured to switch, when there exists a first audio interface between the audio apparatus and a computer apparatus, to using a second audio interface between the audio apparatus and the computer apparatus, the second audio interface being different from the first audio interface. The switching comprises: receiving, via the first audio interface, combined audio data and non-audio data, the non-audio data comprising a request to switch to using the second audio interface; obtaining the request from the data; and, in response to obtaining the request, transmitting to the computer apparatus a confirmation of switching to using the second audio interface. The audio apparatus and the computer apparatus are described and claimed.