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公开(公告)号：JP2018535580A
公开(公告)日：2018-11-29
申请号：JP2018514948
申请日：2016-09-09
Applicant: クゥアルコム・インコーポレイテッド , QUALCOMM INCORPORATED
CPC classification number: G06F11/261 , G06F11/263 , G06F11/27 , H04L1/241
Abstract: 様々な態様が、オンチップハードウェアエラー生成器コンポーネントを説明する。いくつかのケースでは、ハードウェアエラー生成器コンポーネントは、同じチップ内に含まれる2つのコンポーネント間のデータパスに接続する。エラーシミュレーション入力を受信すると、ハードウェアエラー生成器コンポーネントは、エラー状態をシミュレートするデータパターンを挿入することによってデータパス上で伝送されているデータを変更する。代わりに、または追加で、ハードウェアエラー生成器は、伝送されるデータビットの1つまたは複数をランダムに改変する。 【選択図】図3a
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公开(公告)号：JP3892911B2
公开(公告)日：2007-03-14
申请号：JP52210698
申请日：1997-11-03
Applicant: ドイッチェ テレコム アーゲー
Inventor： シェーファー，アンドレアス , ヘルレ，クリスチャン , ルドルフ，ディートマー
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公开(公告)号：JPS59193658A
公开(公告)日：1984-11-02
申请号：JP6702483
申请日：1983-04-18
Applicant: Nec Corp
Inventor： OOTANI SUSUMU
CPC classification number: H04L27/2275 , H04L1/241
Abstract: PURPOSE: To decrease the estimate error of a true line error rate by extimating the line code error stably even if the operating point of a nonlinear element existing on a transmission line is fluctuated by means of a branching circuit, a carrier regenerating circuit, a phase modulation and demodulation circuit and a comparator circuit.
CONSTITUTION: An input modulation wave from a terminal 401 is branched into three by a signal branching circuit, and one branched output signal is inputted to the carrier regenerating circuit 403. Then, an output signal of the circuit 403 is branched 404, and one of the other branched signals by the circuit 402 is phase- demodulated by the phase demodulating circuit 405 by using the branched signal. Further, the other signal branched at the circuit 404 is inputted to the phase modulator 407 and subject to phase modulation by an output signal of an oscillator 408. Moreover, the remaining signal branched by the circuit 402 is phase- demodulated 406 by using a phase modulating signal outputted from the circuit 407. Then, the output of the circuit 405 is taken as a reference, the output of the phase demodulating circuit 406 is compared 409 and its output is outputted from an output terminal as a pseudo error signal.
COPYRIGHT: (C)1984,JPO&JapioAbstract translation: 目的：即使传输线上存在的非线性元件的工作点由分支电路，载波再生电路，载波再生电路，相位变化，波导，也可以稳定地延长线路误码率，从而降低真线误码率的估计误差 调制解调电路和比较电路。 构成：通过信号分支电路将端子401的输入调制波分支为三路，并将一条分支输出信号输入到载波再生电路403.然后，电路403的输出信号分支为404，其中之一为 电路402的其他分支信号通过使用分支信号由相位解调电路405进行相位解调。 此外，在电路404处分支的另一信号被输入到相位调制器407，并通过振荡器408的输出信号进行相位调制。此外，由电路402分支的剩余信号通过使用相位被相位解调406 调制信号。然后，将电路405的输出作为参考，比较409相位解调电路406的输出，并将其输出作为伪误差信号从输出端输出。
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公开(公告)号：JPS59171230A
公开(公告)日：1984-09-27
申请号：JP4634283
申请日：1983-03-17
Applicant: Mitsubishi Electric Corp
Inventor： FUJINO TADASHI
CPC classification number: H04L1/241
Abstract: PURPOSE:To attain accurate measurement of pseudo error rate by using a regenerated clock phase-shifted so as to identify and regenerate a receiving data signal thereby controlling the sampling point of time of a regenerating device always in the vicinity of the maximum point of the eye opening. CONSTITUTION:An up-down counter CT11 is reset by a reset signal l3 and a pseudo error pulse sampled by a lead clock from a phase shifter 6 at an identifying and regenerating device 3 is inputted to an UP terminal of the CT11 via an EXOR9. On the other hand, the pseudo error pulse sampled by a lag clock from the phase shifter 7 at an identifying and regenerating device 4 is inputted to a DOWN terminal of the CT11 via an EXOR10. The CT11 controls the output phase of the phase shifter 8 based on the count value for a prescribed time and a threshold value. Thus, the output phase of the phase shifter 8 is controlled so that the sampling point of the regenerating device 2 may be at the maximum point of the eye opening at all times.
Abstract translation: 目的：通过使用相移的再生时钟来精确测量伪误码率，从而识别和再生接收数据信号，从而控制再生设备的采样时间始终在眼睛最大点附近 开幕。 构成：通过复位信号l3复位升降计数器CT11，通过EXOR9将来自识别再生装置3的来自移相器6的引导时钟采样的伪误差脉冲输入到CT11的UP端子。 另一方面，由识别再生装置4的来自移相器7的滞后时钟采样的伪误差脉冲通过EXOR10输入到CT11的DOWN端。 CT11基于规定时间的计数值和阈值来控制移相器8的输出相位。 因此，控制移相器8的输出相位，使得再生装置2的采样点始终处于眼睛打开的最大点。
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公开(公告)号：JPS5918917B2
公开(公告)日：1984-05-01
申请号：JP7661476
申请日：1976-06-30
Applicant: Ericsson L M Pty Ltd
Inventor： PIITAA RUURU , OOEN MEESU , AANESUTO JIMAA
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Patent Agency Ranking46.发明申请SELF-ERROR INJECTION TECHNIQUE FOR POINT-TO-POINT INTERCONNECT TO INCREASE TEST COVERAGE 审中-公开点对点自检错误注入技术可以提高测试覆盖率
公开(公告)号：WO2017053093A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/051092
申请日：2016-09-09
Applicant: QUALCOMM INCORPORATED
Inventor： CHENG, Scott , KHAN, Raheel , BANGA, Kanwal
IPC: H04L1/24
CPC classification number: G06F11/261 , G06F11/263 , G06F11/27 , H04L1/241
Abstract: Various aspects describe an on-chip, hardware error-generator component. In some cases, the hardware error-generator component connects to a data path between two components contained within a same chip. Upon receiving an error simulation input, the hardware error-generator component modifies data being transmitted on the data path by inserting a data pattern that simulates an error condition. Alternately or additionally, the hardware error-generator randomly alters one or more of the transmitted data bits.
Abstract translation: 各种方面描述了片上硬件错误发生器组件。 在某些情况下，硬件错误发生器组件连接到同一芯片中包含的两个组件之间的数据路径。 在接收到错误模拟输入时，硬件错误发生器组件通过插入模拟错误状况的数据模式来修改在数据路径上传输的数据。 替代地或另外地，硬件错误发生器随机地改变一个或多个所发送的数据位。
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公开(公告)号：WO00067392A1
公开(公告)日：2000-11-09
申请号：PCT/JP2000/002786
申请日：2000-04-27
IPC: H04B3/46 , H04L1/00 , H04L1/20 , H04L1/24 , H04L27/10 , H04L27/18 , H04L29/14 , H04N5/00 , H04N7/10 , H04N17/00 , H04N21/61 , H04N21/647
Abstract: A method for evaluating the quality of a cable circuit which transmits a digital modulation signal in both directions is provided with a step of extracting a noise signal of an upstream line from either a node that connects a head-end of the cable circuit whose quality is to be evaluated and the cable circuit or a node that connects a tap-off and the cable circuit, a step of generating a pseudo-random signal, a step of outputting a test carrier by modulating a carrier signal of a predetermined frequency with the pseudo-random signal, a step of outputting an output signal of the sun of the noise signal of the upstream line and the test carrier, a step of selectively receiving the signal of the predetermined frequency from the output signal and demodulating the same, and a step of evaluating the bit error rate by comparing the demodulated signal and the pseudo-random signal for every bit.
Abstract translation: 提供了一种用于评估在两个方向上发送数字调制信号的电缆电路的质量的方法，该方法从连接电缆电路的前端的节点提取上行线路的噪声信号，该节点的质量为 被评估的电缆电路或连接分接电缆和电缆电路的节点，产生伪随机信号的步骤，通过用伪随机信号调制预定频率的载波信号来输出测试载波的步骤 随机信号，输出上游线路和测试载波的噪声信号的太阳输出信号的步骤，从输出信号中选择性地接收预定频率的信号并对其进行解调的步骤，以及步骤 通过比较每个位的解调信号和伪随机信号来评估误码率。
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公开(公告)号：WO00028709A1
公开(公告)日：2000-05-18
申请号：PCT/JP1999/006295
申请日：1999-11-11
CPC classification number: H04L1/00 , H04L1/0003 , H04L1/241
Abstract: A dummy error addition circuit for adding a dummy error to an orthogonal modulation symbol data, wherein a value based on a specified bit error rate is loaded to count clock signals at a counter (11), a carrier of the counter (11) stores outputs from a PN data generator (21) in a shift register (22), outputs from a PN comparison circuit (3) when stored data agree with count values of the counter (11) are recognized as error pulses, a bit selector (40) randomly selects, on receiving error pulses and based on outputs from a PN data generator (41), bits to which to add errors in an orthogonal modulation data, e.g. a PSK modulation symbol data, at intervals based on a bit error rate, and bits selected from the orthogonal modulation data are inverted in a bit inversion circuit (5) for outputting to thereby add errors.
Abstract translation: 一种用于向正交调制符号数据添加虚拟错误的虚拟误差加法电路，其中基于指定误码率的值被加载以对计数器（11）计数时钟信号，计数器（11）的载波存储输出 当与计数器（11）的计数值一致的存储数据被识别为误差脉冲时，从PN比较电路（3）输出来自移位寄存器（22）中的PN数据发生器（21）的位选择器（40） 在接收到错误脉冲并基于PN数据生成器（41）的输出时，随机地选择在正交调制数据中添加错误的位，例如 基于比特误码率的间隔的PSK调制符号数据和从正交调制数据中选择的比特在比特反相电路（5）中被反转，从而输出错误。
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公开(公告)号：WO98036609A1
公开(公告)日：1998-08-20
申请号：PCT/CA1998/000087
申请日：1998-02-04
CPC classification number: H04Q11/0478 , H04L1/241 , H04L1/243 , H04L2012/5628
Abstract: Telecommunications networks require a variety of tests to monitor their proper operations. Performance monitoring (and fault detection) of the physical layer of a transmission system is one of them and is usually accomplished by using a bit error rate test (BERT). The BERT of the invention uses modified ATM idle cells to conduct one-way, bidirectional and loopback BERT. ATM idle cells are loaded with BERT data at the transmit end and recovered at the receive end. The BERT data are processed according to the different data rates of the ATM transmission system. Performance parameters are derived from the received BERT data. The disclosure describes a method as well as a system for performing such a test.
Abstract translation: 电信网络需要进行各种测试来监控其正常运行。 传输系统的物理层的性能监测（和故障检测）是其中之一，通常通过使用误码率测试（BERT）来完成。 本发明的BERT使用修改的ATM空闲小区来进行单向，双向和环回BERT。 ATM空闲单元在发送端装入BERT数据，并在接收端恢复。 根据ATM传输系统的不同数据速率处理BERT数据。 性能参数是从接收到的BERT数据导出的。 本公开描述了一种方法以及用于执行这种测试的系统。
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50.发明申请METHOD FOR SUPPRESSING INTERFERENCE SIGNALS DURING TRANSMISSION OF DIGITAL SIGNALS 审中-公开输电数字方法用信号AT噪声抑制
公开(公告)号：WO1998021849A1
公开(公告)日：1998-05-22
申请号：PCT/EP1997006042
申请日：1997-11-03
Applicant: DEUTSCHE TELEKOM AG , RUDOLPH, Dietmar , HÖRLLE, Christian , SCHÄFER, Andreas
Inventor： DEUTSCHE TELEKOM AG
IPC: H04L01/24
Abstract: The invention relates to a method for transmitting digital signals, especially in AM bands (radio broadcast bands). A high level modulation, preferably 32 ASPK or 64 ASPK is used for data blocks which are to be transmitted. The invention is characterized by periodic measurement of interference at the receiver end and the subtraction of thus determined interference signals from reception signals.
Abstract translation: 本发明涉及一种方法，用于在AM带（无线频带）传输数字信号，尤其是，被用于要发送的数据块的高级别调制，优选为32或APSK 64 APSK。 它的特征在于，由其和接收信号的某些干扰被减去制成的故障的接收侧时间上周期性测量。
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