公开(公告)号：WO2015073646A1

公开(公告)日：2015-05-21

申请号：PCT/US2014/065412

申请日：2014-11-13

Applicant: QUALCOMM INCORPORATED

Inventor： KHAN, Raheel ,  MUJAHID, Fahad Ali

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F9/30181 ,  G06F7/76 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8053

Abstract: Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The reordering circuitry is configured to reorder output vector data sample sets from execution units as a result of performing vector processing operations in-flight while the output vector data sample sets are being provided over the data flow paths from the execution units to the vector data memory to be stored. In this manner, the output vector data sample sets are stored in the reordered format in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in the execution units.

Abstract translation: 公开了在执行单元和向量数据存储器之间的数据流路径中采用重新排序电路的向量处理引擎（VPE），以提供存储到向量数据存储器中的输出矢量数据的飞行中排序。 还公开了相关矢量处理器系统和方法。 在VPE中的执行单元和向量数据存储器之间的数据流路径中提供重排序电路。 重新排序电路被配置为作为执行向量处理操作的结果，在执行单元中重新排序输出向量数据样本集，同时输出向量数据样本集被提供在从执行单元到向量数据存储器的数据流路径上 被存储。 以这种方式，输出矢量数据样本集以重新排序的格式存储在矢量数据存储器中，而不需要额外的后处理步骤，这可能会延迟在执行单元中执行的后续矢量处理操作。

公开(公告)号：WO2014164367A1

公开(公告)日：2014-10-09

申请号：PCT/US2014/022162

申请日：2014-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： KHAN, Raheel

IPC: G06F15/78 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/7867 ,  G06F15/8053 ,  Y02D10/12 ,  Y02D10/13

Abstract: Embodiments disclosed herein include vector processing engines (VPEs) having programmable data path configurations for providing multi-mode vector processing. Related vector processors, systems, and methods are also disclosed. The VPEs include a vector processing stage(s) configured to process vector data according to a vector instruction executed in the vector processing stage. Each vector processing stage includes vector processing blocks each configured to process vector data based on the vector instruction being executed. The vector processing blocks are capable of providing different vector operations for different types of vector instructions based on data path configurations. Data paths of the vector processing blocks are programmable to be reprogrammable to process vector data differently according to the particular vector instruction being executed. In this manner, a VPE can be provided with its data paths configuration programmable to execute different types of functions based on data path configuration according to the vector instruction being executed.

Abstract translation: 本文公开的实施例包括具有用于提供多模式向量处理的可编程数据路径配置的向量处理引擎（VPE）。 还公开了相关的矢量处理器，系统和方法。 VPE包括被配置为根据在矢量处理阶段中执行的矢量指令来处理矢量数据的矢量处理级。 每个矢量处理级包括矢量处理块，每个矢量处理块被配置为基于正在执行的矢量指令来处理矢量数据。 向量处理块能够基于数据路径配置为不同类型的向量指令提供不同的向量操作。 矢量处理块的数据路径可编程为可重新编程，以根据正在执行的特定向量指令不同地处理矢量数据。 以这种方式，可以为VPE提供可编程的数据路径配置，以根据正在执行的向量指令，基于数据路径配置来执行不同类型的功能。

公开(公告)号：WO2012045044A1

公开(公告)日：2012-04-05

申请号：PCT/US2011/054432

申请日：2011-09-30

Applicant: QUALCOMM INCORPORATED ,  KHAN, Raheel ,  CHAN, Joseph C. ,  SHALEV, Ron ,  ZAMAN, Naveed U.

Inventor： KHAN, Raheel ,  CHAN, Joseph C. ,  SHALEV, Ron ,  ZAMAN, Naveed U.

IPC: G06F9/52 ,  G06F9/50

CPC classification number: G06F9/544

Abstract: Techniques are provided which may be implemented in various methods and/or apparatuses that to provide a tasking system buffer interface capability to interface with a plurality of shared processes/engines.

Abstract translation: 提供了技术，其可以在提供任务系统缓冲器接口能力以与多个共享进程/引擎接口的各种方法和/或装置中实现。

公开(公告)号：WO2017053093A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/051092

申请日：2016-09-09

Applicant: QUALCOMM INCORPORATED

Inventor： CHENG, Scott ,  KHAN, Raheel ,  BANGA, Kanwal

IPC: H04L1/24

CPC classification number: G06F11/261 ,  G06F11/263 ,  G06F11/27 ,  H04L1/241

Abstract: Various aspects describe an on-chip, hardware error-generator component. In some cases, the hardware error-generator component connects to a data path between two components contained within a same chip. Upon receiving an error simulation input, the hardware error-generator component modifies data being transmitted on the data path by inserting a data pattern that simulates an error condition. Alternately or additionally, the hardware error-generator randomly alters one or more of the transmitted data bits.

Abstract translation: 各种方面描述了片上硬件错误发生器组件。 在某些情况下，硬件错误发生器组件连接到同一芯片中包含的两个组件之间的数据路径。 在接收到错误模拟输入时，硬件错误发生器组件通过插入模拟错误状况的数据模式来修改在数据路径上传输的数据。 替代地或另外地，硬件错误发生器随机地改变一个或多个所发送的数据位。

公开(公告)号：WO2015073526A1

公开(公告)日：2015-05-21

申请号：PCT/US2014/065200

申请日：2014-11-12

Applicant: QUALCOMM INCORPORATED

Inventor： KHAN, Raheel

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F9/30181 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8076

Abstract: Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations are disclosed. Related vector processor systems and methods are also disclosed. Format conversion circuitry is provided in data flow paths between vector data memory and execution units in the VPE. The format conversion circuitry is configured to convert input vector data sample sets fetched from vector data memory in-flight while the input vector data sample sets are being provided over the data flow paths to the execution units to be processed. In this manner, format conversion of the input vector data sample sets does not require pre-processing, storage, and re-fetching from vector data memory, thereby reducing power consumption and not limiting efficiency of the data flow paths by format conversion pre-processing delays.

Abstract translation: 公开了在向量数据存储器和执行单元之间的数据流路径中采用格式转换电路的矢量处理引擎（VPE），以向输入矢量数据提供转换为执行单元的向量处理操作。 还公开了相关矢量处理器系统和方法。 在VPE中的矢量数据存储器和执行单元之间的数据流路径中提供格式转换电路。 格式转换电路被配置为将输入矢量数据样本集合在数据流路径上提供给要处理的执行单元的同时，将从输入向量数据存储器中取出的输入向量数据样本集合进行转换。 以这种方式，输入向量数据样本集的格式转换不需要从向量数据存储器进行预处理，存储和重新获取，从而通过格式转换预处理来降低功耗并且不限制数据流路径的效率 延迟。

公开(公告)号：WO2014164298A2

公开(公告)日：2014-10-09

申请号：PCT/US2014/021782

申请日：2014-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： KHAN, Raheel

IPC: G06F17/14

CPC classification number: G06F17/142 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8053 ,  G06F2207/382

Abstract: Vector processing engines (VPEs) having programmable data path configurations for providing multi-mode Radix-2 X butterfly vector processing circuits. Related vector processors, systems, and methods are also disclosed. The VPEs disclosed herein include a plurality of vector processing stages each having vector processing blocks that have programmable data path configurations for performing Radix-2 X butterfly vector operations to perform Fast Fourier Transform (FFT) vector processing operations efficiently. The data path configurations of the vector processing blocks can be programmed to provide different types of Radix-2 X butterfly vector operations as well as other arithmetic logic vector operations. As a result, fewer VPEs can provide desired Radix-2 X butterfly vector operations and other types arithmetic logic vector operations in a vector processor, thus saving area in the vector processor while still retaining vector processing advantages of fewer register writes and faster vector instruction execution times over scalar processing engines.

Abstract translation: 具有可编程数据路径配置的矢量处理引擎（VPE），用于提供多模Radix-2X蝴蝶向量处理电路。 还公开了相关的矢量处理器，系统和方法。 本文公开的VPE包括多个矢量处理级，每个矢量处理级具有矢量处理块，该矢量处理块具有用于执行基数-2X蝶矢量运算的可编程数据路径配置，以有效地执行快速傅里叶变换（FFT）矢量处理操作。 矢量处理块的数据路径配置可以被编程为提供不同类型的Radix-2X蝴蝶向量运算以及其他算术逻辑矢量运算。 因此，较少的VPE可以在向量处理器中提供期望的Radix-2X蝴蝶向量操作和其他类型的算术逻辑向量操作，从而节省向量处理器中的区域，同时仍然保留较少寄存器写入和更快矢量指令执行时间的向量处理优点 超标量处理引擎。

公开(公告)号：WO2013109620A1

公开(公告)日：2013-07-25

申请号：PCT/US2013/021726

申请日：2013-01-16

Applicant: QUALCOMM INCORPORATED

Inventor： HSU, Steve H. ,  KHAN, Raheel

IPC: H04L25/03 ,  H04J11/00 ,  H04L27/26

CPC classification number: H04L25/03273 ,  H04J11/005 ,  H04L25/0328 ,  H04L27/2657

Abstract: Methods and apparatus are described for interference cancellation of interference components of a time domain signal in the frequency domain. A time domain sequence is received, and a plurality of overlapping time domain segments is generated from the time domain sequence. Frequency offset compensation to compensate for frequency offset associated with a serving cell is performed in the time domain, and the overlapping time domain segments are then converted to the frequency domain. Additional frequency offset compensation may be performed to compensation for the frequency offset associated with interfering cells.

Abstract translation: 描述了用于在频域中的时域信号的干扰分量的干扰消除的方法和装置。 接收时域序列，并且从时域序列生成多个重叠的时域片段。 在时域中执行用于补偿与服务小区相关联的频率偏移的频率偏移补偿，然后将重叠的时域片段转换为频域。 可以执行额外的频率偏移补偿以补偿与干扰小区相关联的频率偏移。

公开(公告)号：WO2013109617A1

公开(公告)日：2013-07-25

申请号：PCT/US2013/021722

申请日：2013-01-16

Applicant: QUALCOMM INCORPORATED

Inventor： KHAN, Raheel ,  HSU, Steve H.

IPC: H04L25/03

CPC classification number: H04L25/03159

Abstract: Methods and apparatus are described for interference cancellation of interference components of a time domain signal in the frequency domain. A communications device receives a time domain sequence and generates overlapping time domain segments from the time domain sequence. The overlapping time domain segments are then converted to the frequency domain to generate frequency domain representations of the overlapping time domain segments. The frequency domain representations are stored in a residual memory, and interference components are directly removed from the frequency domain representations stored in the residual memory in the frequency domain.

Abstract translation: 描述了用于在频域中的时域信号的干扰分量的干扰消除的方法和装置。 通信设备接收时域序列，并从时域序列生成重叠的时域片段。 然后将重叠的时域片段转换成频域以产生重叠时域片段的频域表示。 频域表示被存储在剩余存储器中，并且干扰分量直接从存储在频域中的残余存储器中的频域表示中去除。

公开(公告)号：EP3411999A1

公开(公告)日：2018-12-12

申请号：EP17707437.4

申请日：2017-02-01

Applicant: Qualcomm Incorporated

Inventor： KHAN, Raheel ,  CHENG, Scott ,  PHILIPPE, Pascal ,  ROMERA, Joaquin

IPC: H04L7/00 ,  G06F13/42 ,  H04B1/40

CPC classification number: G06F13/4291 ,  G06F9/00 ,  G06F13/364 ,  H04B1/40 ,  H04L7/0008 ,  H04L7/046 ,  H04L29/06 ,  H04L49/35 ,  H04L67/2823 ,  H04L69/00 ,  H04L69/22

Abstract: Transmission of data over a serial link based on a unidirectional clock signal is provided. A unidirectional clock signal is generated based on a first clock of a master device. The unidirectional clock signal is sent to a slave device that is connected to the serial link. The master device transmits data to the slave device over the serial link based on the first clock. The slave device receives the unidirectional clock signal from a master device. The slave device transmits data over the serial link to the master device based on the unidirectional clock signal.

公开(公告)号：EP3100158B1

公开(公告)日：2018-08-29

申请号：EP15704884.4

申请日：2015-01-26

Applicant: Qualcomm Incorporated

Inventor： KHAN, Raheel ,  HSU, Steve Hengchen ,  SINGARAVELU, Gayatri

IPC: G06F9/30 ,  H04B1/7115

CPC classification number: H04L25/0212 ,  G06F9/30 ,  G06F9/30036 ,  H04B1/7115 ,  H04B1/7117 ,  H04L25/0204 ,  H04L25/0224

Abstract: Systems and methods for performing a rake-finger operation on a vector processor are described herein. In one embodiment, a method for rake-finger processing comprises loading samples from a register into an execution unit, performing a rake-finger operation on the samples in the execution unit, and writing results from the rake-finger operation to the register. Performing the rake-finger operation comprises performing a finite impulse response (FIR) filter operation, and performing a despread operation, wherein filtered samples from the FIR filter operation are input to the despread operation without going through the register.