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    PROTECTION OF ELECTRON-EMISSIVE ELEMENTS PRIOR TO REMOVING EXCESS EMITTER MATERIAL DURING FABRICATION OF ELECTRON-EMITTING DEVICE
    51.
    发明授权
    PROTECTION OF ELECTRON-EMISSIVE ELEMENTS PRIOR TO REMOVING EXCESS EMITTER MATERIAL DURING FABRICATION OF ELECTRON-EMITTING DEVICE 有权
    电子发射元件之前去除不必要的发光材料，电子发射器件的制备过程中保护

    公开(公告)号：EP1036403B1

    公开(公告)日：2006-11-29

    申请号：EP98954016.6

    申请日：1998-10-27

    Applicant: Candescent Technologies Corporation

    Inventor： KNALL, N., Johan

    IPC: H01J9/02

    CPC classification number: H01J9/025

    Abstract: In a partially finished electron-emitting device having electron-emissive elements (56A) formed at least partially with electrically non-insulating emitter material, electron-emissive element contamination that could result from passage of contaminant material through an excess layer (56B) of the emitter material is inhibited by forming a protective layer (58 or 70) over the excess emitter-material layer before performing additional processing operations on the electron-emitting device. Subsequent to these processing operations, material of the excess and protective layers overlying the electron-emissive elements is removed to expose the electron-emissive elements.

    FLAT PANEL DISPLAY WITH REDUCED ELECTRON SCATTERING EFFECTS
    55.
    发明授权
    FLAT PANEL DISPLAY WITH REDUCED ELECTRON SCATTERING EFFECTS 失效
    与还原的电子TRUST影响平板显示器

    公开(公告)号：EP0862785B1

    公开(公告)日：2002-07-03

    申请号：EP96942041.3

    申请日：1996-11-20

    Applicant: Candescent Technologies Corporation

    Inventor： SPINDT, Christopher, J. ,  FIELD, John, E. ,  HAVEN, Duane, A.

    IPC: H01J31/12 ,  H01J29/02

    CPC classification number: H01J29/327 ,  H01J9/242 ,  H01J29/085 ,  H01J29/864 ,  H01J31/127 ,  H01J2329/8625 ,  H01J2329/863 ,  H01J2329/8665

    Abstract: A flat panel display is disclosed which includes a faceplate with a faceplate interior side, and a backplate including a backplate interior side in an opposing relationship to the faceplate interior side. Side walls are positioned between the faceplate and the backplate. The side walls, faceplate and backplate form an enclosed sealed envelope. A plurality of phosphor subpixels are positioned at the faceplate interior side. A plurality of field emitters are positioned at the backplate interior side. The field emitters emit electrons which strike corresponding phosphor subpixels. A plurality of scattering shields surround each phosphor subpixel and define a subpixel volume. The scattering shields reduce the number of scattered electrons exiting from their corresponding subpixel volume. This reduces the number of scattered electrons from charging internal insulating surfaces in the envelope, as well as striking the non-corresponding phosphor subpixels.

    VOLTAGE RATIO REGULATOR SYSTEM
    56.
    发明公开
    VOLTAGE RATIO REGULATOR SYSTEM 审中-公开
    VOLTSPANNUNGSREGLERSYSTEM

    公开(公告)号：EP1092181A1

    公开(公告)日：2001-04-18

    申请号：EP99912865.5

    申请日：1999-03-23

    Applicant: Candescent Technologies Corporation

    Inventor： DUNPHY, James, C. ,  SCHROPP, Donald, R., Jr.

    IPC: G05F1/00

    CPC classification number: G09G3/22 ,  G09G2300/043 ,  H01J29/028 ,  H01J31/127 ,  H01J2329/8625 ,  H01J2329/864 ,  H01J2329/8645

    Abstract: A voltage ratio regulator circuit (300) for a spacer electrode (140) of a flat panel display screen. Within one implementation of a field emission display (FED) device (100), thin spacer walls (130) are inserted between a high voltage (Vh) faceplate (120) and a backplate (164) to secure these structures are a vacuum is formed between. The faceplate (120) warms relative to the backplate (164) as a result of energy released by a phosphor layer, thereby generating a temperature gradient along the spacer walls (130). The top portion of each spacer wall (130) becomes more conductive with increased temperature and acts to attract electrons that are emitted toward the faceplate (120). To counter this attraction, a spacer electrode (140) is placed along each spacer wall (130) at a height, d, above the backplate (164) and maintained at a voltage, Ve. The spacer electrode (140) at Ve and the high voltage supply (250) at Vh are both coupled to a voltage ratio regulator circuit (300) which maintains the ratio (Ve/Vh) using voltage dividers (R1, R2, R10 and R11, R3), an operational amplifier (310) and other circuitry. The voltage ratio regulator (300) compensates for variations in voltage supply performance. The time constants (R1, C1 and R3, C3) of the voltage ratio regulator circuit (300) is tuned to be near or slightly faster than the time constant of the inherent resistance (RW1, RW2) and capacitance (CW1, CW2) of the spacer wall (130). The invention improves the electron path accuracy for pixels located near spacer walls.

    MULTI-LEVEL CONDUCTIVE MATRIX FORMATION METHOD
    58.
    发明公开
    MULTI-LEVEL CONDUCTIVE MATRIX FORMATION METHOD 失效
    一种用于生产导电的多级矩阵

    公开(公告)号：EP1023635A1

    公开(公告)日：2000-08-02

    申请号：EP98936011.0

    申请日：1998-07-24

    Applicant: Candescent Technologies Corporation

    Inventor： CHANG, David, C. ,  LEARN, Arthur, J. ,  MACKEY, Bob, L. ,  DRUMM, Paul, M. ,  MORRIS, David, L.

    IPC: G03C5/00 ,  H01J9/00

    CPC classification number: G03F7/0035 ,  G03F7/0007 ,  H01J9/185 ,  H01J9/242 ,  H01J2329/863

    Abstract: A method for forming a three-dimensional multi-level conductive matrix structure for a flat panel display device. In one embodiment, the present invention forms first pixel separating structures across a surface of a faceplate of a flat panel display. The first pixel separating structures separate adjacent first sub-pixel regions. In this embodiment, the first pixel separating structures are formed by applying a first layer of photo-imagable material across the surface of the faceplate. Next, portions of the first layer of photo-imagable material are removed to leave regions of the first layer of photo-imagable material covering respective first sub-pixel regions. Then, a first layer of conductive material is applied over the surface of the faceplate such that the first layer conductive material is disposed between the aforementioned regions of the first layer of photo-imagable material. The present invention then removes the regions of the first layer of photo-imagable material leaving only first pixel separating structures formed of the first layer of conductive material, disposed between the first sub-pixel regions. The present invention performs similar steps in order to form second pixel separating structures between the second sub-pixel regions. The second pixel separating structures are formed substantially orthogonally oriented with respect to the first pixel separating structures and, in the present embodiment, have a different height than the first pixel separating structures. In so doing, a three-dimensional multi-level conductive matrix structure is formed.

    FIELD EMITTER FABRICATION USING MEGASONIC ASSISTED LIFT-OFF
    59.
    发明公开
    FIELD EMITTER FABRICATION USING MEGASONIC ASSISTED LIFT-OFF 失效
    制造场发射装置BY MEGA SOUND支持的分离

    公开(公告)号：EP1019937A1

    公开(公告)日：2000-07-19

    申请号：EP98906245.0

    申请日：1998-02-11

    Applicant: Candescent Technologies Corporation

    Inventor： WILLIAMS, Dale, A.

    IPC: H01J9/02

    CPC classification number: H01J9/025

    Abstract: A method for removing a lift-off layer (214) and an overlying closure layer (218) formed during manufacture of a field emitter structure having at least one emitter (220) on a substrate (202) comprising: a) immersing the field emitter structure in an etchant which attacks the lift-off layer (214) and b) activating a vibrational transducer (410) immersed in the etchant to subject the lift-off and closure layers to vibrational forces which aid in removing these layers (214, 218) from the emitter structure (210, 206, 220). The transducer (410) is preferably a megasonic transducer. After rinsing etchant from the emitter structure, the emitter structure may be dried using an alcohol-based fluid displacement drying process.

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