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    Controlled impedance transistor switch circuit
    55.
    发明公开
    Controlled impedance transistor switch circuit 失效
    Transistorschaltkreis mit gesteuerter Impedanz。

    公开(公告)号：EP0599631A1

    公开(公告)日：1994-06-01

    申请号：EP93309370.0

    申请日：1993-11-24

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Parsons, Brian Jeremy ,  Simpson, Robert John

    IPC: H03K17/16

    CPC classification number: H03K17/167 ,  G11C7/1051 ,  H03K17/164

    Abstract: An output driver circuit comprises a plurality of parallel pull up and pull down circuits (30,31,32,41,42,43) each comprising at least one transistor switch (35,51) switchable between on and off states and circuitry (36,50) operable to maintain a desired resistance in the circuit when the transistor switch is switched on, and switch actuating circuitry including time delay circuitry (53,54,55) for effecting a sequence of transistor switching operations in said pull-up and pull-down circuits with a time delay between successive operations, each operation effecting simultaneous switching of a transistor in one pull-up circuit (30) and one pull-down circuit (41), whereby the output impedance is stabilised during a change in signal on the output terminal (15).

    Abstract translation: 输出驱动器电路包括多个并联上拉和下拉电路（30,31,32,41,42,43），每个并行上拉和下拉电路包括可在导通和截止状态之间切换的至少一个晶体管开关（35,51）和电路（36 ，50），其可操作以在所述晶体管开关导通时保持所述电路中的期望电阻;以及开关致动电路，包括用于在所述上拉和下拉中实现晶体管切换操作的时间延迟电路（53,54,55） 下降电路在连续操作之间具有时间延迟，每个操作实现在一个上拉电路（30）和一个下拉电路（41）中同时切换晶体管，由此在信号变化期间输出阻抗稳定 输出端子（15）。

    Video signal processing for ghost cancellation
    56.
    发明公开
    Video signal processing for ghost cancellation 失效
    Verarbeitungssystem zurGeisterbildauslöschungeines Videosignales。

    公开(公告)号：EP0518580A2

    公开(公告)日：1992-12-16

    申请号：EP92305211.2

    申请日：1992-06-08

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Bramley, Richard Gavin

    IPC: H04N5/21

    CPC classification number: H04N5/211

    Abstract: Apparatus for filtering ghost signals from a video signal sequence comprises storage circuitry (14) for storing a representation of the reference signal, input circuitry (16) for inputting video signals from the video signal sequence, comparison circuitry (12) for comparing the stored representation of the reference signal with the reference signal received in the video signal sequence at said input circuitry thereby to detect ghosts, filter coefficient generating circuitry connected to said comparison circuitry to generate a frequency domain representation of filter coefficients dependent on ghost signals detected, a forward fourier transform pipeline (22) connected to said input circuitry (16) to form a frequency domain representation of data in the video signal sequence received by said input circuitry, product forming circuitry (35) for forming in the frequency domain a product of the filter coefficients with the frequency domain representation of the data in the video signal sequence, and an inverse fourier transform pipeline (45) connected to said product forming circuitry (35) for receiving said product and transforming it to provide an output in the time domain representing said video signal sequence from which detected ghost signals have been removed.

    Abstract translation: 用于从视频信号序列过滤重影信号的设备包括用于存储参考信号的表示的存储电路（14），用于从视频信号序列输入视频信号的输入电路（16），用于比较存储的表示 参考信号与在所述输入电路处的视频信号序列中接收的参考信号相关联，从而检测重影，连接到所述比较电路的滤波器系数产生电路，以产生取决于检测到的重影信号的滤波器系数的频域表示，前向傅里叶 连接到所述输入电路（16）的变换流水线（22）以形成由所述输入电路接收的视频信号序列中的数据的频域表示，产品形成电路（35）用于在频域中形成滤波器系数 与视频信号中的数据的频域表示 以及连接到所述产品形成电路（35）的反向傅立叶变换管线（45），用于接收所述产品并对其进行变换，以在时域中提供表示所检测到的重影信号已被去除的所述视频信号序列的输出。

    Message routing
    57.
    发明公开
    Message routing 失效
    消息路由

    公开(公告)号：EP0405989A3

    公开(公告)日：1992-10-14

    申请号：EP90307108.2

    申请日：1990-06-28

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： May, Michael David ,  Thompson, Peter William ,  Parsons, Brian Jeremy ,  Walker, Christopher Paul Hulme

    IPC: H04L12/56

    CPC classification number: H04L49/25 ,  G06F15/17375 ,  H04L45/00 ,  H04L45/06 ,  H04L45/40 ,  H04L49/101 ,  H04L49/106 ,  H04L49/254 ,  H04L49/30 ,  H04L49/3018 ,  H04L49/3027

    Abstract: A routing switch (1) includes an input (4a) for receiving serial packets from a source node in a computer network, a plurality of outputs (6a...6n), switch circuitry (10) for selectively interconnecting said input to a selected one of said outputs and header reading circuitry (22) for reading the header portion of a packet received at the input prior to receiving all of the packet. The switch also has a random header generator (24) which produces header portions generated at random which are then read by the header reading circuitry. The header reading circuitry is coupled to the switch circuitry (10) to connect to said input one of said outputs in dependence on said random header. The random header portion is then discarded at the routing switch identified thereby to reveal the original header. There is also provided a computer network, having a plurality of computer devices and at least one routing switch, and a method of routing messages through such a network.

    Semiconductor chip packages
    58.
    发明公开
    Semiconductor chip packages 失效
    半导体芯片包

    公开(公告)号：EP0430458A3

    公开(公告)日：1992-06-03

    申请号：EP90312152.3

    申请日：1990-11-06

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Wakefield, Elwyn Paul Michael ,  Walker, Christopher Paul Hulme

    IPC: H01L23/50 ,  H01L25/10

    CPC classification number: H01L23/50 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor chip package (2) comprising at least one semiconductor chip disposed in a package and a plurality of first and second pins (18,20) extending from the package, which first pins are electrically connected to the at least one semiconductor chip and are adapted to conduct signals between the at least one semiconductor chip and external circuitry, the first pins being divided into a plurality of groups, each group representing a respective signal type, and which second pins are not electrically connected to the at least one semiconductor chip, the first pins of at least one group and the second pins being asymmetrically disposed along edges (14,16) of the package and the remaining groups of first pins being symmetrically disposed along edges of the package. The invention also provides a stacked module of the semiconductor chip packages.

    Timing control for a memory
    59.
    发明公开
    Timing control for a memory 失效
    一个记忆的时序控制

    公开(公告)号：EP0422939A3

    公开(公告)日：1991-09-04

    申请号：EP90311168.0

    申请日：1990-10-11

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Ferris, Andrew Timothy ,  Work, Gordon Stirling

    IPC: G11C7/00

    CPC classification number: G11C7/22 ,  G11C7/14 ,  Y10S438/926

    Abstract: A memory circuit comprises a plurality of memory cells (2) arranged in rows and columns, the cells in each row being connected to a common word line (4) and the cells in each column being connected between a pair of bit lines (6,8) across which a voltage differential is developed when a memory cell is accessed to be read; and a timing circuit (16) for producing a timing signal to control further circuitry in dependence on said voltage differential achieving a predetermined value. The memory circuit has a dummy bit line connected to a column of dummy cells, each dummy cell having the same structure as a memory cell. A plurality of said dummy cells (22) has a bit value stored therein and is connected to a dummy word line and the remainder of said dummy cells are rendered inactive, whereby on addressing of the dummy wordline simultaneously with the wordline of an accessed cell, a predetermined number of dummy cells discharges via the dummy bit line so that the voltage developed on the dummy bit line is a fixed multiple of the voltage differential developed between the bit lines of the accessed cell. The timing circuit (16) is connected to receive the voltage differential on the dummy bit line (18).

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