公开(公告)号：WO2007041469A2

公开(公告)日：2007-04-12

申请号：PCT/US2006/038390

申请日：2006-09-27

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  CERIO, Frank, M., Jr.

Inventor： CERIO, Frank, M., Jr.

CPC classification number: C23C14/541 ,  C23C14/046 ,  C23C14/345 ,  C23C14/358 ,  H01L21/2855 ,  H01L21/76876 ,  H01L21/76879

Abstract: An iPVD system (200A, 200B) is programmed to deposit uniform material (115, 120), such as a metallic material, into high aspect ratio nano-sized features (110) on semiconductor substrates (105) using a process that enhances the feature filling (130C) compared to the field deposition (106), while maximizing the size of the grain features in the deposited material opening (140) at the top of the feature during the process. Sequential deposition and etching are provided by controlling DC and high density power levels and other parameters.

Abstract translation: iPVD系统（200A，200B）被编程为使用增强特征的过程将诸如金属材料的均匀材料（115,120）沉积到半导体衬底（105）上的高纵横比纳米尺寸特征（110）中 在该过程期间，在特征顶部使沉积材料开口（140）中的颗粒特征的尺寸最大化，从而与场沉积（106）相比填充（130℃）。 通过控制DC和高密度功率等级和其他参数来提供顺序沉积和蚀刻。

公开(公告)号：WO2007040704A1

公开(公告)日：2007-04-12

申请号：PCT/US2006/026688

申请日：2006-07-10

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  SUZUKI, Kenji

Inventor： SUZUKI, Kenji

IPC: H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76843 ,  C23C16/18 ,  C23C16/56 ,  H01L21/28556 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76874

Abstract: A method (400, 401 ) for integrating a Ru layer (504, 614) with bulk Cu (510, 622) in semiconductor manufacturing. The method includes depositing a Ru layer (504, 614) onto a substrate (25, 125, 502, 601 ) in a chemical vapor deposition process, modifying the deposited Ru layer (504, 614) by oxidation, or nitridation, or a combination thereof, depositing an ultra thin Cu layer (508, 618) onto the modified Ru layer (506, 616), and plating a Cu layer (510, 622) onto the ultra thin Cu layer (508, 618).

Abstract translation: 一种用于在半导体制造中集成Ru层（504,614）与体Cu（510,622）的方法（400,401）。 该方法包括在化学气相沉积工艺中将Ru层（504,614）沉积到衬底（25,125,502,601）上，通过氧化或氮化或组合来改变沉积的Ru层（504,614） 在所述改性Ru层（506,616）上沉积超薄Cu层（508,618），以及将Cu层（510,622）镀覆到所述超薄Cu层（508,618）上。

公开(公告)号：WO2006104853A1

公开(公告)日：2006-10-05

申请号：PCT/US2006/010606

申请日：2006-03-23

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  SUZUKI, Kenji

Inventor： SUZUKI, Kenji

IPC: H01L21/768 ,  H01L23/532 ,  C23C16/16 ,  C23C16/448

CPC classification number: H01L23/53238 ,  C23C16/045 ,  C23C16/16 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76871 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low-temperature chemical vapor deposition process for depositing low- resistivity ruthenium metal layers (440, 460) that can be used as barrier/seed layers in Cu metallization schemes. The method (300) includes providing a substrate (25, 125) in a process chamber (10, 110) of a deposition system (1, 100), forming a process gas containing a ruthenium carbonyl precursor vapor and a CO-containing gas, and exposing the substrate (25, 125) to the process gas to deposit a low-resistivity ruthenium metal layer (440, 460) on the substrate (25, 125) by a thermal chemical vapor deposition process, where the substrate (25, 125) is maintained at a temperature between about 100°C and about 300°C during the exposing. A semiconductor device containing the ruthenium metal layer (440, 460) formed on a patterned substrate (402, 404, 406, 408) containing one or more vias or trenches (430), or combinations thereof, is provided.

Abstract translation: 一种用于沉积可用作Cu金属化方案中的阻挡/种子层的低电阻钌金属层（440,460）的低温化学气相沉积工艺。 方法（300）包括在沉积系统（1,100）的处理室（10,110）中提供衬底（25,125），形成含有羰基钌前驱体蒸气和含CO气体的工艺气体， 以及将所述衬底（25,125）暴露于所述工艺气体，以通过热化学气相沉积工艺在所述衬底（25,125）上沉积低电阻钌金属层（440,460），其中所述衬底（25,125 ）在曝光期间保持在约100℃和约300℃之间的温度。 提供了包含形成在包含一个或多个通孔或沟槽（430）的图案化衬底（402,404,406,408）或其组合上的钌金属层（440,460）的半导体器件。

公开(公告)号：WO2006104687A1

公开(公告)日：2006-10-05

申请号：PCT/US2006/009225

申请日：2006-03-14

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  FINK, Steven

Inventor： FINK, Steven

IPC: H01J37/32 ,  H01L21/00

CPC classification number: H01L21/67069 ,  H01J37/32091 ,  H01J37/32495 ,  H01J37/32532

Abstract: An upper electrode assembly (UEL) (42) is supported in an insulator (50) in an opening (43) in the top of an etch chamber (12) in which large diameter substrates are processed with a flange of the UEL overlying the chamber wall (46) around the opening with the insulator in between so that the insulator experiences primarily compressive and minimal shear loads. The electrode (42) nonetheless fills the otherwise vacuum space between the UEL (42) and the chamber (12) wall above a shield ring (65) that covers the insulator and portions of the adjacent UEL face and chamber wall.

Abstract translation: 上部电极组件（UEL）（42）被支撑在蚀刻室（12）的顶部中的开口（43）中的绝缘体（50）中，其中大直径衬底被处理，其中UEL的凸缘覆盖在腔室 壁（46）围绕开口，绝缘体在其间，使得绝缘体主要经受压缩和最小剪切载荷。 然而，电极（42）仍然填满覆盖绝缘体和相邻UEL面和室壁的部分的屏蔽环（65）上方的UEL（42）和室（12）壁之间的另外的真空空间。

公开(公告)号：WO2006057710A1

公开(公告)日：2006-06-01

申请号：PCT/US2005/035583

申请日：2005-10-03

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  SUZUKI, Kenji ,  GUIDOTTI, Emmanuel ,  LEUSINK, Gerrit, J. ,  HARA, Masamichi ,  KUROIWA, Daisuke

Inventor： SUZUKI, Kenji ,  GUIDOTTI, Emmanuel ,  LEUSINK, Gerrit, J. ,  HARA, Masamichi ,  KUROIWA, Daisuke

IPC: C23C16/448

CPC classification number: C23C16/16 ,  C23C16/4481

Abstract: A replaceable precursor tray for use with a high conductance, multi-tray solid precursor evaporation system (50, 150, 300, 300') coupled with a high conductance vapor delivery system is described for increasing deposition rate by increasing exposed surface area of solid precursor. The multi-tray solid precursor evaporation system (50, 150, 300, 300') is configured to be coupled to the process chamber (10, 110) of a thin film deposition system (1, 100), and it includes a base tray (330) with one or more stackable upper trays (340). Each tray (330, 340) is configured to support and retain film precursor (350) in, for example, solid powder form or solid tablet form. Additionally, each tray (330, 340) is configured to provide for a high conductance flow of carrier gas over the film precursor (350) while the film precursor (350) is heated. For example, the carrier gas flows inward over the film precursor (350), and vertically upward through a flow channel (318) within the stackable trays (370, 370') and through an outlet (322) in the solid precursor evaporation system (50, 150, 300, 300').

Abstract translation: 用于与高电导，多托盘固体前体蒸发系统（50,150,300,300'）结合高电导蒸气输送系统使用的可替换的前体托盘被描述为通过增加固体前体的暴露表面积来提高沉积速率 。 多托盘固体前体蒸发系统（50,150,300,300'）被配置为耦合到薄膜沉积系统（1,100）的处理室（10,110），并且其包括底盘 （330）具有一个或多个可堆叠的上托盘（340）。 每个托盘（330,340）被配置为以例如固体粉末形式或固体片剂形式支撑并保持膜前体（350）。 另外，每个托盘（330,340）构造成在膜前体（350）被加热的同时提供载气在膜前体（350）上的高电导流。 例如，载气在膜前体（350）内向内流动，并且垂直向上流过可堆叠托盘（370,370'）内的流动通道（318）并且通过固体前体蒸发系统中的出口（322） 50,150,300,300'）。

公开(公告)号：WO2006039321A1

公开(公告)日：2006-04-13

申请号：PCT/US2005/034761

申请日：2005-09-27

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  BABIC, Darko ,  WHITE, Carl, L. ,  PARENT, Wayne, M.

Inventor： BABIC, Darko ,  WHITE, Carl, L. ,  PARENT, Wayne, M.

IPC: H01L21/00 ,  B01D11/02 ,  B01J3/00 ,  B08B7/00

CPC classification number: H01L21/67028 ,  B08B7/0021 ,  H01L21/67023

Abstract: A method and system (100) is described for introducing chemistry into a high pressure fluid for treating a substrate. In particular, the method includes dispersing the chemistry throughout the volume of high pressure fluid in order to promote mixing of the two or more fluids, while the high pressure fluid is circulating through a high pressure processing system (110).

Abstract translation: 描述了用于将化学物质引入用于处理基底的高压流体中的方法和系统（100）。 特别地，该方法包括将化学物质分散在整个体积的高压流体中，以便在高压流体循环通过高压处理系统（110）时促进两种或多种流体的混合。

公开(公告)号：WO2006039029A2

公开(公告)日：2006-04-13

申请号：PCT/US2005/030841

申请日：2005-08-31

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  WAJDA, Cory

Inventor： WAJDA, Cory

CPC classification number: H01L21/02181 ,  C23C16/40 ,  C23C16/401 ,  C23C16/405 ,  C23C16/5096 ,  C23C16/52 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

Abstract: A method for forming a thin complete high-k layer (106, 207) for semiconductor applications. The method includes providing a substrate (25, 102, 202, 406) in a process chamber (10, 402), depositing a thick complete high-k layer (206) on the substrate (25, 102, 202, 406), and thinning the deposited high-k layer (206) to form a thin complete high-k layer (106, 207) on the substrate (25, 102, 202, 406). Alternately, the substrate (25, 102, 202, 406) can contain an interface layer (104, 204) between the substrate (25, 102, 202, 406) and the high-k layer (106, 207). The thinning can be performed by exposing the thick high-k layer (206) to a reactive plasma etch process or, alternately, a plasma process capable of modifying a portion of the thick high-­k layer (206) and subsequently removing the modified portion (206a) of the thick high-k layer (206) using wet processing.

Abstract translation: 一种形成用于半导体应用的薄的完整高k层（106,207）的方法。 该方法包括在处理室（10,402）中提供衬底（25,102,202,406），在衬底（25,102,202,406）上沉积厚的完整的高k层（206），以及 使沉积的高k层（206）变薄以在衬底（25,102,202,406）上形成薄的完整的高k层（106,207）。 或者，衬底（25,102,202,406）可以包含在衬底（25,102,202,406）和高k层（106,207）之间的界面层（104,204）。 可以通过将厚的高k层（206）暴露于反应性等离子体蚀刻工艺或者替代地，能够修饰厚的高k层（206）的一部分并随后去除修饰部分的等离子体处理 （206）的湿式加工（206a）。

公开(公告)号：WO2006039026A1

公开(公告)日：2006-04-13

申请号：PCT/US2005/030663

申请日：2005-08-30

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  KAWAMURA, Kohei ,  ASANO, Akira ,  MIYATANI, Koutarou ,  HILLMAN, Joseph, T. ,  PALMER, Bentley

Inventor： KAWAMURA, Kohei ,  ASANO, Akira ,  MIYATANI, Koutarou ,  HILLMAN, Joseph, T. ,  PALMER, Bentley

IPC: H01L21/3105 ,  H01L21/312 ,  H01L21/768 ,  H01L21/3205

CPC classification number: H01L21/76826 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/31058 ,  H01L21/3127 ,  H01L21/32051 ,  H01L21/76814

Abstract: A method for treating a fluoro-carbon dielectric film (4, 26) for integration of the dielectric film (4, 26) into a semiconductor device. The method includes providing a substrate (2, 22, 105) having a fluoro-carbon film (4, 26) deposited thereon, the film (4, 26) having an exposed surface (6) containing contaminants (8), and treating the exposed surface (6) with a supercritical carbon dioxide fluid to clean the exposed surface (6) of the contaminants (8) and provide surface termination. The supercritical carbon dioxide treatment improves adhesion and electrical properties of film structures (1, 20) containing a metal-containing film (12, 30) formed on the surface of the fluoro-carbon dielectric film (4, 26).

Abstract translation: 一种用于处理用于将电介质膜（4,26）整合到半导体器件中的氟 - 碳电介质膜（4,66）的方法。 该方法包括提供具有沉积在其上的氟碳膜（4,26）的基底（2,102,105），所述薄膜（4,26）具有含有污染物（8）的暴露表面（6），并处理 暴露的表面（6）用超临界二氧化碳流体清洁污染物（8）的暴露表面（6）并提供表面终止。 超临界二氧化碳处理改善了在氟碳电介质膜（4,66）的表面上形成的含有金属的膜（12,30）的膜结构（1,20）的粘附性和电性能。

公开(公告)号：WO2006007228A1

公开(公告)日：2006-01-19

申请号：PCT/US2005/018847

申请日：2005-05-27

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  VUKOVIC, Miro

Inventor： VUKOVIC, Miro

IPC: H01J37/32

CPC classification number: H01J37/32477 ,  H01J37/321

Abstract: A plasma processing system (10) and method provide an internal coil (40) in a vacuum chamber (12) for maintaining a high density plasma (30) therein in a manner that may have a less restrictive requirement on metal flux shielding than when the shield (42) protects a dielectric window. The shield also shields the coil from plasma heat load. The coil need not be actively cooled. Some metal is allowed to pass through the shield and deposit on the coil. This leads to a thinner shield with less complicated slots (43) than for shields in external coil configurations. Good FT transparency of the shield is a result of the much simpler shield shape. The coil is not sputtered and is thus not consumable. The coil is enclosed in a small conductive space, reducing its inductance, resulting in reduced coil current and voltage, in turn simplifying the design and construction of the tuning network (22a) and RF connectors. Stiffeners (45) support the coil and are profiled to avoid formation of conductive paths forming from metal deposits.

Abstract translation: 等离子体处理系统（10）和方法在真空室（12）内提供内部线圈（40），用于在其中维持高密度等离子体（30），其方式可能对金属通量屏蔽的限制要求比 屏蔽（42）保护电介质窗口。 屏蔽还可以屏蔽线圈的等离子体热负荷。 线圈不需要主动冷却。 一些金属被允许通过屏蔽并沉积在线圈上。 这导致具有比外部线圈配置中的屏蔽更少的复杂插槽（43）的更薄的屏蔽。 盾牌的良好FT透明度是屏蔽形状简单得多的结果。 线圈没有被溅射，因此不是消耗品。 线圈被封闭在小的导电空间中，减小其电感，从而减少线圈电流和电压，从而简化调谐网络（22a）和RF连接器的设计和构造。 加强件（45）支撑线圈并成型以避免形成由金属沉积物形成的导电路径。

公开(公告)号：WO2006007005A1

公开(公告)日：2006-01-19

申请号：PCT/US2005/013885

申请日：2005-04-22

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  GALE, Glenn, W. ,  HILLMAN, Joseph, T. ,  JACOBSON, Gunilla ,  PALMER, Bentley

Inventor： GALE, Glenn, W. ,  HILLMAN, Joseph, T. ,  JACOBSON, Gunilla ,  PALMER, Bentley

IPC: H01L21/311

CPC classification number: H01L21/31133 ,  H01L21/31111

Abstract: A method and system for processing a substrate (178, 265) in a film removal system (200, 201). The method includes providing the substrate (178, 265) in a substrate chamber (250) of a film removal system (200, 201), where the substrate (178, 265) has a micro-feature containing a dielectric film (182) on a sidewall (183) of the micro-feature (170) and a photoresist film (184) covering a portion the dielectric film (182), and performing a first film removal process using supercritical CO 2 processing to remove the portion (186) of the dielectric film (182) not covered by the photoresist film (184). Following the first film removal process, a second film removal process using supercritical CO 2 processing can be performed to remove the photoresist film (184). Alternately, wet processing can be used to perform one of the first film removal process or the second film removal process.

Abstract translation: 一种用于在膜去除系统（200,201）中处理衬底（178,265）的方法和系统。 该方法包括将衬底（178,265）设置在膜去除系统（200,201）的衬底室（250）中，其中衬底（178,265）具有包含介电膜（182）的微特征 所述微特征（170）的侧壁（183）和覆盖所述电介质膜（182）的一部分的光致抗蚀剂膜（184），并且使用超临界CO