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公开(公告)号：KR100132859B1
公开(公告)日：1998-04-16
申请号：KR1019930025136
申请日：1993-11-24
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: H01L27/10852 , H01L27/10817 , Y10S148/014
Abstract: A fabrication method of cylindrical capacitor is provided to improve capacitance and simplify the process. The method comprises the steps of: forming a first conductive layer(60) on a substrate(10); forming a first pattern(60a) by patterning the first conductive layer(60); forming a spacer(64) at both sidewalls of a second conductive layer(62); forming a second pattern(60a,62a) by etching the second conductive layer(62) and the first pattern(60a) using the spacer(64) as a mask; forming a third conductive layer(66) on the resultant structure; forming a storage electrode(100) by etching the third conductive layer(66); and removing the spacer(64).
Abstract translation: 提供圆柱形电容器的制造方法以改善电容并简化工艺。 该方法包括以下步骤：在衬底（10）上形成第一导电层（60）; 通过图案化第一导电层（60）形成第一图案（60a）; 在第二导电层（62）的两个侧壁处形成间隔物（64）; 通过使用间隔物（64）作为掩模蚀刻第二导电层（62）和第一图案（60a）来形成第二图案（60a，62a）; 在所得结构上形成第三导电层（66）; 通过蚀刻第三导电层（66）形成存储电极（100）; 并移除间隔物（64）。
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Patent Agency Ranking
公开(公告)号：KR1019930014988A
公开(公告)日：1993-07-23
申请号：KR1019920016302
申请日：1992-09-07
Applicant: 삼성전자주식회사
IPC: H01L27/10
Abstract: 본 발명은 반도체 메모리장치의 제조방법에 관한 것으로, 특히, 반도체기판 전면에 도전층을 형성하는 공정, 도전층 전면에 제1물질층을 형성하는 공정, 제1물질층 전면에 반구모양의 그레인을 갖는 다결정 실리콘층을 형성하는 공정, 다결정실리콘을 식각마스크로 하고, 제1물질층을 식각대상물로 한 식각공정을 결과물전면에 행하여 제1물질층패턴을 형성하는 공정, 및 제1물질층패턴을 식각마스크로 하고, 도전층을 식각대상물로 한 이방성식각을 행하여 상기 도전층을 부분적으로 제거하는 공정을 포함하는 고집적 반도체 메모리장치의 커패시터 제조방법을 제공한다. 따라서, 간단한 공정으로 큰 셀커패시턴스를 확보할 수 있으므로 64Mb급 및 256Mb급으로 고집적화 되어가는 반도체 메모리 장치에 적용가능하다.
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公开(公告)号：KR1019930014898A
公开(公告)日：1993-07-23
申请号：KR1019910024193
申请日：1991-12-24
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: 본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히 접촉창이 형성될 영역을 제외한 모든 영역에 형성된 골을 소정의 물질로 채운 후, 상기 접촉창을 형성하고, 이어서 패드를 형성한 후 상기 소정의 물질을 제거하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 접촉창 형성방법을 제공한다.
따라서 굴곡있는 표면상에 도전물질로 된 패턴을 형성할 때 생기는 도전물질의 찌꺼기 발생을 방지할 수 있으므로 신뢰성 있는 반도체 메모리장치 및 메모리장치의 집적도 증가를 달성할 수 있다.-
公开(公告)号：KR1020110132791A
公开(公告)日：2011-12-09
申请号：KR1020100052327
申请日：2010-06-03
Applicant: 삼성전자주식회사
IPC: H01L23/62
CPC classification number: H01L23/5256 , H01L2924/0002 , H01L23/62 , H01L2924/00
Abstract: PURPOSE: A fuse structure and an electrical fuse including the fuse structure and a semiconductor device including the electrical fuse are provided to prevent a re-growth phenomenon by forming a moisture absorption prevention film which surrounds a fuse conductive layer pattern. CONSTITUTION: First and second electrodes(120,130) are extended to a first direction. One end of the first electrode and one end of the second electrode are separated and are faced each other. An insulating layer(200) is formed between the one end of the first electrode and the one end of the second electrode which are faced each other. A conductive film(162) is touched with the first and second electrodes. The conductive film is formed in the top of the insulating layer by overlapping with a part of the first and second electrodes. A third electrode which is extended to a second direction which is vertical with the first direction is formed in the inner side of the insulating layer.
Abstract translation: 目的：提供一种熔丝结构和包括熔丝结构的电熔丝和包括电熔丝的半导体器件，以通过形成围绕熔丝导电层图案的吸湿防止膜来防止再生长现象。 构成：第一和第二电极（120,130）延伸到第一方向。 第一电极的一端和第二电极的一端分离并且彼此面对。 绝缘层（200）形成在第一电极的一端和彼此面对的第二电极的一端之间。 导电膜（162）与第一和第二电极接触。 通过与第一和第二电极的一部分重叠，在绝缘层的顶部形成导电膜。 在绝缘层的内侧形成有延伸到与第一方向垂直的第二方向的第三电极。
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公开(公告)号：KR1020100087915A
公开(公告)日：2010-08-06
申请号：KR1020090006979
申请日：2009-01-29
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242
CPC classification number: H01L28/91 , H01L27/10817 , H01L27/10852
Abstract: PURPOSE: A semiconductor memory device and a manufacturing method thereof are provided to reduce contact resistance by increasing contact area between a storage node contact plug and a lower electrode. CONSTITUTION: A switching element(2) is formed on a semiconductor substrate. A storage contact plug(4) for connecting to the switching element is arranged in an insulation layer. The insulation layer is recessed so that a part of the upper/side surface of the storage contact plug is exposed. A cylindrical storage node(8) includes a lower electrode which is contacted with a part of the exposed upper/side surface of the storage node contact plug.
Abstract translation: 目的：提供半导体存储器件及其制造方法，以通过增加存储节点接触插头和下电极之间的接触面积来降低接触电阻。 构成：在半导体衬底上形成开关元件（2）。 用于连接到开关元件的存储接触插头（4）布置在绝缘层中。 绝缘层凹入，使得存储接触插塞的上/侧表面的一部分露出。 圆筒形存储节点（8）包括与存储节点接触插塞的暴露的上/侧表面的一部分接触的下电极。
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公开(公告)号：KR1020070081640A
公开(公告)日：2007-08-17
申请号：KR1020060013742
申请日：2006-02-13
Applicant: 삼성전자주식회사
Inventor： 박원모
CPC classification number: H01L23/5256 , H01L21/76835 , H01L22/10
Abstract: A semiconductor device and its manufacturing method are provided to etch a test pattern, when the test pattern is offset from a guard ring, by forming the test pattern on the same layer as fuses. A semiconductor device includes plural fuses(112), a guard ring(125), a test pattern(116), first and second pads(126a,126b), and a second interlayer dielectric(120). The fuses are formed on a first interlayer dielectric(110) and apart from one another. The guard ring is formed around the fuses. The test pattern is arranged on the same layer as the fuses and formed around the guard ring. The first and the second pads are arranged on the test pattern and connected to both ends of the test pattern, respectively. The second interlayer dielectric is formed on the first interlayer dielectric and includes a pad window and a fuse window. The pad window exposes the first and the second pads, while the fuse window exposes the fuses.
Abstract translation: 提供半导体器件及其制造方法，通过在与熔丝相同的层上形成测试图案，当测试图案与保护环偏移时，蚀刻测试图案。 半导体器件包括多个熔丝（112），保护环（125），测试图案（116），第一和第二焊盘（126a，126b）和第二层间电介质（120）。 保险丝形成在第一层间电介质（110）上并且彼此分开。 保护环形成在保险丝周围。 测试图案设置在与保险丝相同的层上，并形成在保护环周围。 第一和第二焊盘被布置在测试图案上并且分别连接到测试图案的两端。 第二层间电介质形成在第一层间电介质上，并包括焊盘窗和熔丝窗。 保险丝窗口暴露第一和第二垫，而保险丝窗口暴露出保险丝。
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