公开(公告)号：KR100695306B1

公开(公告)日：2007-03-14

申请号：KR1020010035305

申请日：2001-06-21

Applicant: 삼성전자주식회사

Inventor： 최준후 ,  정관욱

IPC: H01L29/868

Abstract: 기판 위에 금속층을 증착하고 패터닝하여 n+ 오믹 접촉층을 형성하고, 오믹 접촉층 위에 n+ a-Si 층을 형성한다. 다음, n+ a-Si 층 위에 진성 a-Si 층을 형성하고, 진성 a-Si 층 상부에 B
2 H
x + 형태의 이온을 주입하여 진성 a-Si 층 위에 p+ a-Si 층을 형성한다. 다음, p+ a-Si 층 위에 ITO를 증착하고 어닐링하여 p+ 오믹 접촉층을 형성한다. 다음, 기판 위에 질화 규소와 같은 절연 물질로 이루어진 보호막을 형성하고, n+ 오믹 접촉층을 노출시키는 접촉 구멍과 p+ 오믹 접촉층을 노출시키는 접촉 구멍을 형성한다. 다음, 보호막 위에 접촉 구멍을 통해 n+ 오믹 접촉층 및 p+ 오믹 접촉층과 각각 연결되는 데이터 패드와 바이어스 배선을 형성한다. 여기서, p+ a-Si 층을 형성할 때 화학 기상 증착법을 사용하지 않고 이온 주입법을 사용하므로 화학 기상 증착 장비의 오염을 방지하여 유지 보수가 간편해진다. 또한, 이온 주입 시 a-Si 층에 주입되는 이온은 B
2 H
x 인데, H 원소도 함께 주입되므로 이후 어닐링 공정에서 a-Si 막 내의 결점을 보완하여 막질이 향상된다.
PIN 다이오드, 화학 기상 증착법, 이온 주입

公开(公告)号：KR1020040031857A

公开(公告)日：2004-04-14

申请号：KR1020020060461

申请日：2002-10-04

Applicant: 삼성전자주식회사

Inventor： 정관욱

IPC: H05B33/00

CPC classification number: H01L27/3272 ,  H01L27/1259 ,  H01L27/3262

Abstract: PURPOSE: A pixel circuit and a method for manufacturing the same are provided to achieve improved yield rate by arranging a gate line without increasing the area of the circuit part of the pixel. CONSTITUTION: A pixel circuit comprises a gate electrode shielding film(210) and a gate line shielding film(210a) formed on a transparent substrate(200); a first insulating film(220) for exposing a certain part of the gate line shielding film; a poly silicon pattern(230) formed on the first insulating film disposed on the gate electrode shielding film; a second insulating film(240) formed on the resultant structure including the poly silicon pattern, wherein the second insulating film exposes the part of the gate line shielding film exposed by the first insulating film; a gate electrode(260) formed on the second insulating film; a shielding film contact portion(250a) formed in the region exposed by the first and second insulating films; and a gate line(260a) formed on the shielding film contact portion.

Abstract translation: 目的：提供像素电路及其制造方法，以通过布置栅极线而不增加像素的电路部分的面积来实现提高的成品率。 构成：像素电路包括形成在透明基板（200）上的栅电极屏蔽膜（210）和栅极线屏蔽膜（210a）。 用于暴露所述栅极线屏蔽膜的某一部分的第一绝缘膜（220）; 形成在设置在栅电极屏蔽膜上的第一绝缘膜上的多晶硅图案（230） 形成在包括多晶硅图案的所得结构上的第二绝缘膜（240），其中第二绝缘膜暴露由第一绝缘膜暴露的栅极线屏蔽膜的部分; 形成在所述第二绝缘膜上的栅电极; 在由所述第一和第二绝缘膜暴露的区域中形成的屏蔽膜接触部分（250a）; 和形成在屏蔽膜接触部分上的栅极线（260a）。

公开(公告)号：KR1020030039112A

公开(公告)日：2003-05-17

申请号：KR1020010070043

申请日：2001-11-12

Applicant: 삼성전자주식회사

Inventor： 김보성 ,  정관욱 ,  홍완식 ,  김상갑 ,  홍문표

IPC: H01L29/786

CPC classification number: G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  H01L21/76802 ,  H01L21/76804 ,  H01L23/53295 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A contact portion of a semiconductor device and a manufacturing method thereof, and a TFT(Thin Film Transistor) array substrate having the same contact portion for a display apparatus and a manufacturing method of the TFT array panel are provided to be capable of improving the profile of the contact portion by removing an under-cut structure. CONSTITUTION: The first wiring(200) is formed on an upper portion of a substrate(100). A lower layer(310) is formed on the first wiring(200). A photoresist layer pattern(320) is formed on the lower layer(310) by using photosensitive organic material. A contact hole(330) is formed in the lower layer by etching the lower layer using the photoresist layer pattern as an etching mask in order to expose the first wiring. At this time, an under-cut structure is generated under the photoresist layer pattern(320). The edge portion of the lower layer(310) is exposed by partially removing the photoresist layer pattern(320) using an ashing process, so that the under-cut structure is simultaneously removed. The second wiring is formed on the resultant structure and connected with the first wiring(200) through the contact hole(330).

Abstract translation: 目的：提供半导体器件的接触部分及其制造方法以及具有与显示装置相同的接触部分的TFT（薄膜晶体管）阵列基板和TFT阵列面板的制造方法，以能够改善 通过去除底切结构来形成接触部分的轮廓。 构成：第一配线（200）形成在基板（100）的上部。 在第一布线（200）上形成下层（310）。 通过使用光敏有机材料在下层（310）上形成光致抗蚀剂层图案（320）。 通过使用光致抗蚀剂层图案作为蚀刻掩模蚀刻下层，以便露出第一布线，在下层中形成接触孔（330）。 此时，在光致抗蚀剂图案（320）下面产生底切结构。 通过使用灰化处理部分去除光致抗蚀剂层图案（320）来暴露下层（310）的边缘部分，从而同时去除底切结构。 第二布线形成在所得结构上，并且通过接触孔（330）与第一布线（200）连接。

公开(公告)号：KR1020030027302A

公开(公告)日：2003-04-07

申请号：KR1020010060442

申请日：2001-09-28

Applicant: 삼성전자주식회사

Inventor： 홍완식 ,  최준후 ,  김상갑 ,  정관욱 ,  정규하

IPC: G02F1/136

CPC classification number: G02F1/136227 ,  G02F2001/133357 ,  G02F2001/136236 ,  G02F2202/42 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

Abstract: PURPOSE: A thin film transistor substrate using low dielectric constant and a method for manufacturing the same are provided to realize high aperture ratio by solving the problem of parasitic capacity, thereby reducing time required for a process. CONSTITUTION: Gate wiring is formed on an insulating substrate. A gate insulating film(30) is formed on the gate lines. Data wiring crosses the gate wiring on the first insulating film. A plurality of thin film transistors are connected with the gate lines and the data lines. A passivation film(70) composed of an a-Si:C:O film or an a-Si:C:F film which is a low dielectric constant CVD film, is formed on the data wiring, having contact holes(76,78) exposing drain electrodes(66) and data pads(68).

Abstract translation: 目的：提供一种使用低介电常数的薄膜晶体管基板及其制造方法，通过解决寄生电容的问题来实现高开口率，从而缩短了处理所需的时间。 构成：在绝缘基板上形成栅极布线。 栅极绝缘膜（30）形成在栅极线上。 数据线穿过第一绝缘膜上的栅极布线。 多个薄膜晶体管与栅极线和数据线连接。 在具有接触孔（76,78）的数据布线上形成由a-Si：C：O膜或作为低介电常数CVD膜的a-Si：C：F膜构成的钝化膜（70） ）暴露漏电极（66）和数据焊盘（68）。

公开(公告)号：KR1020020069415A

公开(公告)日：2002-09-04

申请号：KR1020010009675

申请日：2001-02-26

Applicant: 삼성전자주식회사

Inventor： 최준후 ,  홍완식 ,  권대진 ,  정관욱

IPC: G02F1/1333

Abstract: PURPOSE: A TFT(Thin Film Transistor) substrate for an LCD device is provided to form a protection layer with an inorganic insulating layer having a lower dielectric constant, thereby improving an opening ratio even when a data line is overlapped with a pixel electrode. CONSTITUTION: Gate wires include the gate line(21) and the gate electrode(22) formed on a substrate. A gate insulating layer(30) covers the gate wires. A semiconductor layer is formed on the gate insulating layer. A data wire includes a data line(61), a source electrode(62), and a drain electrode(63). A protection layer(70) has the first contact hole showing the drain electrode. A pixel electrode(80) is connected to the drain electrode through the first contact hole. A dielectric ratio of the protection layer is composed of an inorganic insulating layer below 3.5.

Abstract translation: 目的：提供一种用于LCD装置的TFT（薄膜晶体管）基板，以形成具有较低介电常数的无机绝缘层的保护层，从而即使当数据线与像素电极重叠时也提高了开口率。 构成：栅极线包括形成在基板上的栅极线（21）和栅电极（22）。 栅极绝缘层（30）覆盖栅极线。 在栅极绝缘层上形成半导体层。 数据线包括数据线（61），源电极（62）和漏电极（63）。 保护层（70）具有示出漏电极的第一接触孔。 像素电极（80）通过第一接触孔与漏电极连接。 保护层的介电比由3.5以下的无机绝缘层构成。