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公开(公告)号：KR1019940006425B1
公开(公告)日：1994-07-20
申请号：KR1019910022465
申请日：1991-12-07
IPC: C04B35/64
Abstract: The high permittivity dielectric ceramics is composed of 86-93 mol% barium titanate and 7-14 mol% calcium stannate as main compounds, and 0.05-0.5 wt.% cuproxide or cupric oxide, 0.05-0.5 wt.% rare earth oxide including lanthanum oxide, neodymium oxide, yttrium oxide, samarium oxide and cerium oxide against the total weight of the main compounds. This dielectric composition is applied to the multilayered ceramic capacitor and enhances the permittivity at room temp. and makes the dielectric ceramics sinter at lower temp. (below 1,150 deg.C).
Abstract translation: 高介电常数介电陶瓷由86-93摩尔％钛酸钡和7-14摩尔％锡酸锡为主要成分，0.05-0.5重量％的氧化亚锡或氧化铜，0.05-0.5重量％稀土氧化物包括镧 氧化物，氧化钕，氧化钇，氧化钐和氧化铈相对于主要化合物的总重量。 该介电组合物被施加到多层陶瓷电容器并且在室温下提高介电常数。 并使电介质陶瓷在较低温度下烧结。 （低于1,150℃）。
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公开(公告)号：KR1019940003970B1
公开(公告)日：1994-05-09
申请号：KR1019910024025
申请日：1991-12-23
IPC: H01G9/00
Abstract: The BaTiO3 base dielectric magnetic composition is little volatile at high temp. and is not toxic for human. The composition comprises: A) 87-93 mol% of barium titanate; B) 7-17 mol% of one or mixture of barium, calcium, lead, and magnesium salt of titanic acid, stannic acid and zirconic acid; C) 0.01-1.0 wt.% (to 10 wt.% of A+B) of cerium oxide; and D) 0.01-2.0 wt.% of copper oxide.
Abstract translation: BaTiO3基介电磁性组合物在高温下几乎没有挥发性。 对人体无毒性。 该组合物包含：A）87-93mol％的钛酸钡; B）钛酸钠，锡酸和锆酸的钡，钙，铅和镁盐的一种或多种混合物为7-17摩尔％; C）0.01-1.0重量％（至10重量％的A + B）氧化铈; 和D）0.01〜2.0重量％的氧化铜。
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Patent Agency Ranking
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公开(公告)号：KR1019910005399B1
公开(公告)日：1991-07-29
申请号：KR1019880011472
申请日：1988-09-05
Applicant: 한국전자통신연구원
Abstract: The self-aligned GaAs FET using double side wall process is manufactured by: depositing the oxide film (105) for outer side wall after forming a dummy gate (104); ion-implantation the n-type impurity after formign outer side wall (106) by dry etching; forming a inner side wall after depositing the oxide film for inner side wall; depositing the gate metal after removing the nitride film (103) of gate region; forming interconnection metal after depositing the oxide film and photoresist (110). The device is useful for high speed operation and has an advantage for reducing the charge capacity of source-gate and the resistance of source.
Abstract translation: 使用双面壁工艺的自对准GaAs FET通过：在形成虚拟栅极（104）之后沉积用于外侧壁的氧化物膜（105）; 通过干蚀刻离子注入形成外侧壁（106）后的n型杂质; 在沉积内壁氧化膜之后形成内侧壁; 在去除栅极区域的氮化物膜（103）之后沉积栅极金属; 在沉积氧化膜和光致抗蚀剂（110）之后形成互连金属。 该装置对于高速运行是有用的，并且具有减小源极的充电容量和源极电阻的优点。
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