公开(公告)号：AU6410294A

公开(公告)日：1994-10-11

申请号：AU6410294

申请日：1994-03-11

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN ,  TEENER MICHAEL D

IPC: H04L12/64 ,  H04L12/801 ,  G06F13/38

Abstract: A dynamic, multi-speed bus architecture comprising a plurality of variable speed, fixed size links for coupling a plurality of devices together in an arbitrary network arrangement in which each device coupled to the bus comprises a novel communications node having a scalable interface for enabling the local hosts of the devices to communicate via the multi-speed bus. The interface provided within each node comprises a first module and a second module interconnected via a fixed speed, variable size bus. The first module is coupled to the local host of a device via a fixed speed, fixed size bus for converting a first data packet received from the local host into a second data packet of an appropriate form for transmission on the fixed speed, variable size bus disposed between the two modules. The second module receives the second data packet and converts it into a third data packet of an appropriate form for transmission onto the variable speed, fixed size link coupling the device to the multi-speed bus. The first and second modules further perform the same conversions in reverse so as to provide for reception of data packets transferred on the multi-speed bus. With such a design of the interface disposed between the link of the multi-speed bus and the local host of each device, it is possible to provide the components for performing the data packet transfer conversions necessary to realize a true dynamic, multi-speed bus in addition to providing a truly scalable architecture having upward compatibility with future devices.

公开(公告)号：AU6230794A

公开(公告)日：1994-08-15

申请号：AU6230794

申请日：1994-01-12

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN ,  TEENER MICHAEL D

IPC: G06F1/26 ,  G06F1/32 ,  G06F3/00

Abstract: The power management system tracks the total amount of power drawn from a bus by devices connected to the bus and to the bus itself, based on the individual operational status of each device. The power manager system also tracks the total amount of power supplied to the bus. From this information the power manager system determines whether a power surplus exists sufficient to allow an additional device to operate or to allow a currently operating device to draw more power. Power usage requests received from devices connected to the bus are granted or denied by the power management system based on the determination of available power. The power management system additionally is capable of sequencing the use of several devices to allow the devices to each operate while maintaining the total power draw within an acceptable range. The system provides for efficient use of a limited amount of power to allow operation of more devices than conventionally allowed with a bus. The system also can activate power supply devices which are off-line via soft-power-on commands to increase to total amount of power available. The system is advantageously implemented with any bus system having devices drawing power from the bus from power supplies providing limited power.

公开(公告)号：AU5954094A

公开(公告)日：1994-07-19

申请号：AU5954094

申请日：1993-12-16

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN

IPC: G06F15/16 ,  G06F13/00 ,  G06F13/14 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64 ,  H04L29/12

Abstract: A node identification system is described for use in a computer system in which the various components of the system are interconnected via nodes on a communications bus. Once the topology of the nodes has been resolved into an acyclic directed graph, each node may be assigned a non-predetermined unique address. Each node having a plurality of ports has an apriori assigned priority for port selection. Each child node connected to a parent is allowed to respond in the predetermined sequence depending upon the port through which it is connected to its parent. Each node in the graph will announce its presence according to its location in the graph. Each receives an address incremented from the previous addresses assigned, thereby insuring uniqueness. The same mechanism may be implemented to allow each node in turn to broadcast information on the bus concerning the parameters of its local host. Likewise, additional information may be conveyed from each node concerning connections to other nodes thereby allowing a host system to generate a map of the resolved topology including any information about disabled links which may be used for redundancy purposes.

公开(公告)号：CA2503597A1

公开(公告)日：1994-07-07

申请号：CA2503597

申请日：1993-12-16

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN

IPC: G06F15/16 ,  G06F13/00 ,  G06F13/14 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64 ,  H04L29/12

Abstract: A node identification system is described for use in a computer system in which the various components of the system are interconnected via nodes on a communications bus. Once the topology of the nodes has been resolved into an acyclic directed graph, each node may be assigned a non-predetermined unique address. Each node having a plurality of ports has an a priori assigned priority for port selection. Each child node connected to a parent is allowed to respond in the predetermined sequence depending upon the port through which it is connected to its parent. Each node in the graph will announce its presence according to its location in the graph. Each receives an address incremented from the previous addresses assigned, thereby insuring uniqueness. The same mechanism may be implemented to allow each node in turn to broadcast information on the bus concerning the parameters of its local host. Likewise, additional information may be conveyed from each node concerning connections to other nodes thereby allowing a host system to generate a map of the resolved topology including any information about disabled links which may be used for redundancy purposes.

公开(公告)号：CA2503335A1

公开(公告)日：1994-07-07

申请号：CA2503335

申请日：1993-12-16

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN

IPC: G06F13/368 ,  G06F13/00 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64

Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent-child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.

公开(公告)号：CA2408532A1

公开(公告)日：1994-07-07

申请号：CA2408532

申请日：1993-12-16

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN

IPC: G06F15/16 ,  G06F13/00 ,  G06F13/14 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64 ,  H04L29/12

Abstract: A node identification system is described for use in a computer system in which the various components of the system are interconnected via nodes on a communications bus. Once the topology of the nodes has been resolved into an acyclic directed graph, each node may be assigned a non-predetermined unique address. Each node having a plurality of ports has an apriori assigned priority for port selection. Each child node connected to a parent is allowed to respond in the predetermined sequence depending upon the port through which it is connected to its parent. Each node in the graph will announce its presence according to its location in the graph. Each receives an address incremented from the previous addresses assigned, thereby insuring uniqueness. The same mechanism may be implemented to allow each node in turn to broadcast information on the bus concerning the parameters of its local host. Likewise, additional information may be conveyed from each node concerning connections to other nodes thereby allowing a host system to generate a map of the resolved topology including any information about disabled links which may be used for redundancy purposes.

公开(公告)号：CA2151368A1

公开(公告)日：1994-07-07

申请号：CA2151368

申请日：1993-12-16

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN

IPC: G06F15/16 ,  G06F13/00 ,  G06F13/14 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64 ,  H04L29/12

Abstract: A node identification system is described for use in a computer system in which the various components of the system are interconnected via nodes on a communications bus. Once the topology of the nodes has been resolved into an acyclic directed graph, each node may be assigned a non-predetermined unique address. Each node having a plurality of ports has an apriori assigned priority for port selection. Each child node connected to a parent is allowed to respond in the predetermined sequence depending upon the port through which it is connected to its parent. Each node in the graph will announce its presence according to its location in the graph. Each receives an address incremented from the previous addresses assigned, thereby insuring uniqueness. The same mechanism may be implemented to allow each node in turn to broadcast information on the bus concerning the parameters of its local host. Likewise, additional information may be conveyed from each node concerning connections to other nodes thereby allowing a host system to generate a map of the resolved topology including any information about disabled links which may be used for redundancy purposes.

公开(公告)号：DE69334202T2

公开(公告)日：2009-01-22

申请号：DE69334202

申请日：1993-12-16

Applicant: APPLE COMPUTER

Inventor： VAN BRUNT ROGER ,  OPRESCU FLORIN

IPC: G06F13/378 ,  G06F13/40 ,  H03K19/0175 ,  H03M5/16 ,  H03M5/18 ,  H04L25/02 ,  H04L25/49

Abstract: The present invention provides a method and apparatus for transmitting NRZ data signals across an interface comprising an isolation barrier disposed between two devices interconnected via a bus. The apparatus comprises a signal differentiator for receiving an NRZ data signal and outputting a differentiated signal. A driver comprising a tri-state gate has a first input the data signal and as a second input the differentiated signal for enabling the tri-state gate when the differentiated signal is high. A bias voltage is applied to an output of the tri-state gate to derive as output a transmission signal for transmission via the bus across the interface between the two devices. In this way, the transmission signal output from the first device comprises an intermediate transmission signal corresponding to the bias voltage when the tri-state gate is disabled, a height transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is high, and a low transmission signal when the tri-state gate is enabled and the first input to the tri-state gate is low. A Schmidt trigger is provided as a receiver in the second device for receiving an input the transmission signal and outputting a reconstituted data signal corresponding to the synchronized data signal.

公开(公告)号：DE69333798T2

公开(公告)日：2006-03-09

申请号：DE69333798

申请日：1993-12-16

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN

IPC: G06F13/368 ,  G06F13/00 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64

Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgement priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always asserts its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initilialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.

公开(公告)号：CA2151369C

公开(公告)日：2004-02-10

申请号：CA2151369

申请日：1993-12-16

Applicant: APPLE COMPUTER

Inventor： OPRESCU FLORIN

IPC: G06F13/368 ,  G06F13/00 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L12/40 ,  H04L12/44 ,  H04L12/56 ,  H04L12/64

Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one nod e designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each nod e may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. T he root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around th e nodes according to the above-described predetermined port priority scheme. Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.