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公开(公告)号：US20200027861A1
公开(公告)日：2020-01-23
申请号：US16585147
申请日：2019-09-27
Applicant: Apple Inc.
Inventor： Jun Zhai
IPC: H01L25/065 , H01L23/00 , H01L23/498 , H01L23/50 , H01L25/16 , H01L23/31 , H01L25/00 , H01L49/02 , H01L23/528 , H01L21/78 , H01L21/683 , H01L21/768 , H01L21/56
Abstract: A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization.
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公开(公告)号：US10056384B2
公开(公告)日：2018-08-21
申请号：US15420572
申请日：2017-01-31
Applicant: Apple Inc.
Inventor： Jared L. Zerbe , Emerson S. Fang , Jun Zhai , Shawn Searles
IPC: H01L21/02 , H01L27/10 , H01L23/48 , H01L23/13 , H01L23/64 , H01L23/00 , H01L25/065 , H01L25/16 , H01L25/18 , H01L23/498 , H01G4/228 , H01L49/02 , H01L25/10 , H01L23/50
CPC classification number: H01L27/101 , H01G4/228 , H01L23/13 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L23/642 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/18 , H01L28/40 , H01L2224/0401 , H01L2224/13025 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16227 , H01L2224/16265 , H01L2224/32225 , H01L2224/45099 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00012 , H01L2924/00014 , H01L2924/1033 , H01L2924/12042 , H01L2924/1205 , H01L2924/1427 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/15153 , H01L2924/15159 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/157 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104 , H01L2924/00 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.
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公开(公告)号：US09935087B2
公开(公告)日：2018-04-03
申请号：US15405046
申请日：2017-01-12
Applicant: Apple Inc.
Inventor： Jun Zhai , Kunzhong Hu
IPC: H01L25/00 , H01L25/10 , H01L23/31 , H01L21/56 , H01L23/538 , H01L23/00 , H01L25/065
CPC classification number: H01L25/105 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/5389 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/24011 , H01L2224/24105 , H01L2224/24225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/82005 , H01L2224/82101 , H01L2224/82106 , H01L2224/83101 , H01L2224/83855 , H01L2224/83862 , H01L2224/83874 , H01L2224/92125 , H01L2224/92225 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/1443 , H01L2924/1451 , H01L2924/14511 , H01L2224/83 , H01L2224/82 , H01L2224/81 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/19
Abstract: Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level molding and fan out structure, and a second level molding and fan out structure between the first and third levels. The second level molding and fan out structure includes back-to-back facing die, with a front surface of each die bonded to a redistribution layer.
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公开(公告)号：US09883822B2
公开(公告)日：2018-02-06
申请号：US15181229
申请日：2016-06-13
Applicant: Apple Inc.
Inventor： Milind S. Bhagavat , Jun Zhai
IPC: G06K9/00 , A61B5/117 , A61B5/1172 , A61B5/053 , H01L27/146
CPC classification number: A61B5/1172 , A61B5/053 , A61B2562/0214 , A61B2562/182 , G06K9/0002 , H01L27/14634 , H01L27/14636
Abstract: A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate.
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公开(公告)号：US20170156002A1
公开(公告)日：2017-06-01
申请号：US15005908
申请日：2016-01-25
Applicant: Apple Inc.
Inventor： Caleb C. Han , Jun Zhai , Tongbi T. Jiang
CPC classification number: H04R1/14 , H04R1/04 , H04R1/1041 , H04R1/46 , H04R19/005 , H04R19/04 , H04R31/006 , H04R2201/107
Abstract: MEMS microphone and vibration sensor dies and packages are described. In an embodiment, a MEMS microphone and vibration sensor die includes a die substrate, a MEMS microphone on the die substrate and a MEMS vibration sensor on the die substrate. The MEMS vibration sensor may include a plurality of beams with different proof masses corresponding to different resonant frequencies, wherein the different proof masses comprise a same material as the die substrate.
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Patent Agency Ranking
公开(公告)号：US09661411B1
公开(公告)日：2017-05-23
申请号：US15005908
申请日：2016-01-25
Applicant: Apple Inc.
Inventor： Caleb C. Han , Jun Zhai , Tongbi T. Jiang
CPC classification number: H04R1/14 , H04R1/04 , H04R1/1041 , H04R1/46 , H04R19/005 , H04R19/04 , H04R31/006 , H04R2201/107
Abstract: MEMS microphone and vibration sensor dies and packages are described. In an embodiment, a MEMS microphone and vibration sensor die includes a die substrate, a MEMS microphone on the die substrate and a MEMS vibration sensor on the die substrate. The MEMS vibration sensor may include a plurality of beams with different proof masses corresponding to different resonant frequencies, wherein the different proof masses comprise a same material as the die substrate.
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公开(公告)号：US20170141088A1
公开(公告)日：2017-05-18
申请号：US15405046
申请日：2017-01-12
Applicant: Apple Inc.
Inventor： Jun Zhai , Kunzhong Hu
IPC: H01L25/10 , H01L23/31 , H01L25/00 , H01L23/538 , H01L23/00 , H01L25/065 , H01L21/56
CPC classification number: H01L25/105 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/5389 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/24011 , H01L2224/24105 , H01L2224/24225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/82005 , H01L2224/82101 , H01L2224/82106 , H01L2224/83101 , H01L2224/83855 , H01L2224/83862 , H01L2224/83874 , H01L2224/92125 , H01L2224/92225 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/1443 , H01L2924/1451 , H01L2924/14511 , H01L2224/83 , H01L2224/82 , H01L2224/81 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/19
Abstract: Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level molding and fan out structure, and a second level molding and fan out structure between the first and third levels. The second level molding and fan out structure includes back-to-back facing die, with a front surface of each die bonded to a redistribution layer.
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公开(公告)号：US09559081B1
公开(公告)日：2017-01-31
申请号：US14935310
申请日：2015-11-06
Applicant: Apple Inc.
Inventor： Kwan-Yu Lai , Jun Zhai , Kunzhong Hu
IPC: H01L25/065 , H01L23/31 , H01L23/48 , H01L21/56 , H01L21/683 , H01L25/00 , H01L23/00 , H01L21/768
CPC classification number: H01L25/0657 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L21/7684 , H01L23/147 , H01L23/3107 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/5389 , H01L24/80 , H01L24/89 , H01L25/0652 , H01L25/0655 , H01L25/10 , H01L25/105 , H01L25/50 , H01L2221/68327 , H01L2224/80895 , H01L2224/80896 , H01L2225/06541 , H01L2225/06548 , H01L2924/181 , H01L2924/186
Abstract: Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.
Abstract translation: 描述了封装和3D裸片堆叠过程。 在一个实施例中，封装包括结合到包括封装在氧化物层中的第一级管芯的第一封装级的第二级管芯晶体管和延伸穿过氧化物层的多个通孔氧化物通孔（TOV）。 在一个实施例中，TOV和第一级模具具有大约20微米或更小的高度。
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公开(公告)号：US09548288B1
公开(公告)日：2017-01-17
申请号：US14966482
申请日：2015-12-11
Applicant: Apple Inc.
Inventor： Vidhya Ramachandran , Chonghua Zhong , Shawn Searles , Jun Zhai , Young Doo Jeon , Huabo Chen
IPC: H01L25/16 , H01L23/528 , H01L23/50 , H01L21/78 , H01L23/00 , H01L21/768 , H01L25/00
CPC classification number: H01L25/16 , H01L21/768 , H01L21/78 , H01L23/50 , H01L23/528 , H01L24/20 , H01L24/97 , H01L2224/12105 , H01L2224/16265 , H01L2224/97 , H01L2924/10253 , H01L2924/14 , H01L2924/1427 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/145 , H01L2924/14511 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/30107 , H01L2224/81
Abstract: A system that includes an integrated circuit die and a power supply decoupling unit is disclosed. The system includes an integrated circuit die, and interconnection region, and a decoupling unit. The integrated circuit die includes a plurality of circuits, which each include multiple devices interconnected using wires fabricated on a first plurality of conductive layers. The interconnection region includes multiple solder balls, and multiple conductive paths, each of which includes wires fabricated on a second plurality conductive layers. At least one solder ball is connected to an Input/Output terminal of a first circuit of the plurality of circuits via one of the conductive paths. The decoupling unit may include a plurality of capacitors and a plurality of terminals. Each terminal of the decoupling unit may be coupled to a respective power terminal of a second circuit of the plurality of circuits via the conductive paths.
Abstract translation: 公开了一种包括集成电路管芯和电源去耦单元的系统。 该系统包括集成电路管芯和互连区域以及去耦单元。 集成电路管芯包括多个电路，每个电路包括使用在第一多个导电层上制造的导线互连的多个器件。 互连区域包括多个焊球，以及多个导电路径，每个导电路径包括制造在第二多个导电层上的导线。 至少一个焊球通过导电路径之一连接到多个电路中的第一电路的输入/输出端子。 去耦单元可以包括多个电容器和多个端子。 去耦单元的每个端子可以经由导电路径耦合到多个电路中的第二电路的相应电源端子。
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公开(公告)号：US20160358889A1
公开(公告)日：2016-12-08
申请号：US14730171
申请日：2015-06-03
Applicant: Apple Inc.
Inventor： Kwan-Yu Lai , Jun Zhai , Kunzhong Hu , Flynn P. Carson
IPC: H01L25/065 , H01L23/31 , H01L21/768 , H01L21/56 , H01L25/00 , H01L23/48 , H01L23/528
CPC classification number: H01L21/768 , H01L21/568 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/92 , H01L24/96 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/06181 , H01L2224/12105 , H01L2224/16227 , H01L2224/2518 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/1421 , H01L2924/1431 , H01L2924/1434 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19106
Abstract: Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a first redistribution layer (RDL) and a second RDL, and a second level die is mounted on a top side of the first redistribution layer. In an embodiment, the first level die is an active die, less than 50 μm thick.
Abstract translation: 描述了包括通过硅通孔（TSV）的嵌入式裸片的封装。 在一个实施例中，包括TSV的第一级裸片被嵌入在第一重分配层（RDL）和第二RDL之间，并且第二级管芯安装在第一再分布层的顶侧。 在一个实施例中，第一级模具是小于50μm厚的有源管芯。
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