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    COMMUNICATION TRANSMITTER USING OFFSET PHASE-LOCKED-LOOP
    52.
    发明专利
    COMMUNICATION TRANSMITTER USING OFFSET PHASE-LOCKED-LOOP 未知

    公开(公告)号：CA2503070A1

    公开(公告)日：2004-05-13

    申请号：CA2503070

    申请日：2003-10-31

    Applicant: GCT SEMICONDUCTOR INC

    Inventor： LEE JEONG-WOO ,  LEE KYEONGHO ,  PARK JOONBAE ,  SONG EUNSEOK ,  LEE KANG-YOON

    IPC: H03C3/09 ,  H04L27/20 ,  H04L27/04 ,  H04L27/12

    Abstract: A translational-loop transmitter generates RF signals using at most one phas e- locked-loop (PLL) circuit. In one embodiment, a single PLL generates two loc al oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type o f modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under the se conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is use d to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. In still other embodiments, a transmitter signal i s generated without using any phase-locked-loop circuits. This is accomplished by generating an intermediate frequency signal using a crystal oscillator, a nd then using a frequency divider in a feedback loop to generate a control sign al for adjusting the voltage-controlled oscillator to the carrier frequency. By minimizingthe number of phase-locked-loop circuits in the transmitter, the size, cost, and power requirements of mobile handsets may be significantly reduced.

    AN RF FRONT END WITH REDUCED CARRIER LEAKAGE
    53.
    发明专利
    AN RF FRONT END WITH REDUCED CARRIER LEAKAGE 未知

    公开(公告)号：CA2492860A1

    公开(公告)日：2004-02-05

    申请号：CA2492860

    申请日：2003-07-28

    Applicant: GCT SEMICONDUCTOR INC

    Inventor： SONG EUNSEOK ,  LEE SEUNG-WOOK ,  LEE KYEONGHO ,  LEE JEONG-WOO ,  PARK JOONBAE

    IPC: H04B1/28 ,  H04B1/52 ,  H04B1/00 ,  H04B1/26

    Abstract: A method and apparatus that provide a frequency conversion in a radio frequency front-end are disclosed, including a frequency divider (407) that divides an input signal frequency by a predetermined value to produce an output signal frequency (417); and a frequency mixer (405, 406) that mixes t he output signal frequency (417) with a carrier signal frequency to produce a converted signal frequency, which is substantially equal to a difference between the output signal frequency (417) and the carrier signal frequency. The predetermined value and the input signal frequency are selected such tha t the carrier signal frequency is not substantially equivalent to an integer multiple of the output signal frequency (417). The method and apparatus can be used in a wireless communication receiver including wireless communication systems and wireless LAN systems.

    LC OSCILLATOR WITH WIDE TUNING RANGE AND LOW PHASE NOISE
    54.
    发明专利
    LC OSCILLATOR WITH WIDE TUNING RANGE AND LOW PHASE NOISE 未知

    公开(公告)号：AU2003234612A1

    公开(公告)日：2003-12-22

    申请号：AU2003234612

    申请日：2003-06-05

    Applicant: GCT SEMICONDUCTOR INC

    Inventor： KOO YIDO ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

    IPC: H03B5/08 ,  H03B1/00 ,  H03B5/12 ,  H03L7/099 ,  H03L7/08

    Abstract: A voltage-controlled oscillator including an active oscillator circuit, an inductor, and capacitive circuits is disclosed. The capacitive circuits are selectively turned on and off to control the frequency of the voltage-controlled oscillator. Particularly, the inductor and the capacitors in the capacitive circuits form LC circuits that provide feedback to the active oscillator circuit. To avoid damage to the switches in the capacitive circuits, the capacitive circuits further comprise resistors. The resistors can be configured in several different ways so that the voltage-controlled oscillator can have a high degree of reliability, and a wide tuning range with constant phase noise performance.

    APPARATUS AND METHOD OF OSCILLATING WIDEBAND FREQUENCY
    57.
    发明申请
    APPARATUS AND METHOD OF OSCILLATING WIDEBAND FREQUENCY 审中-公开
    振荡频率的装置和方法

    公开(公告)号：WO2006036749A3

    公开(公告)日：2006-09-28

    申请号：PCT/US2005034021

    申请日：2005-09-21

    Applicant: GCT SEMICONDUCTOR INC ,  PARK JOONBAE ,  LEE SEUNG-WOOK ,  LEE JEONG-WOO ,  LEE KYEONGHO

    Inventor： PARK JOONBAE ,  LEE SEUNG-WOOK ,  LEE JEONG-WOO ,  LEE KYEONGHO

    IPC: H03L7/08

    CPC classification number: H03L7/113 ,  H03L7/087 ,  H03L7/10 ,  H03L7/187

    Abstract: An apparatus for oscillating a frequency, which comprises a phase lock loop, see fig. 5, a variable frequency divider() is shown, that divides a first frequency (Fout) signal by a division ratio to generate a second frequency signal, this based on a comparison of reference frequency clock input (Fref) and feedback input to phase/frequency detector (510). A charge pump (520) and loop filter (530) are shown with a divider (550) that divides the second frequency signal (355) to allow the correct feedback frequency to be realized. The VCO (540) inherently has a resonant circuit including the capacitors to be selected and a corresponding control voltage to set the frequency of operation as well as an active circuit (320) for proper gain.

    Abstract translation: 用于振荡频率的装置，其包括锁相环，参见图1。 如图5所示，示出了可变分频器（），其将第一频率（Fout）信号除以分频比以产生第二频率信号，这是基于参考频率时钟输入（Fref）和反相输入到相位/ 频率检测器（510）。 示出了电荷泵（520）和环路滤波器（530），其具有分频器（550），其划分第二频率信号（355）以允许实现正确的反馈频率。 VCO（540）固有地具有包括要选择的电容器的谐振电路和用于设置操作频率的相应控制电压以及用于适当增益的有源电路（320）。

    SYSTEM AND METHOD FOR SUPPRESSING NOISE IN A PHASE-LOCKED LOOP CIRCUIT
    58.
    发明申请
    SYSTEM AND METHOD FOR SUPPRESSING NOISE IN A PHASE-LOCKED LOOP CIRCUIT 审中-公开
    用于抑制锁相环电路中的噪声的系统和方法

    公开(公告)号：WO2004040898A3

    公开(公告)日：2004-09-02

    申请号：PCT/US0333709

    申请日：2003-10-23

    Applicant: GCT SEMICONDUCTOR INC ,  AHN YOUNGHO ,  SONG EUNSEOK ,  KOO YIDO ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

    Inventor： AHN YOUNGHO ,  SONG EUNSEOK ,  KOO YIDO ,  LEE JEONG-WOO ,  PARK JOONBAE ,  LEE KYEONGHO

    IPC: H03L7/197 ,  H03L7/06

    CPC classification number: H03L7/1978

    Abstract: A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals may be removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

    Abstract translation: 用于改善频率发生器的信噪比的系统和方法抑制了由于内部发生器电路中的失配而产生的相位噪声和噪声。 这是利用调制方案实现的，该调制方案将发生器的环路带宽之外的寄生噪声信号移位。 当以这种方式移动时，噪声信号可以使用例如沿着发生器的信号路径定位的滤波器被完全移除或以任何期望的程度移除。 在一个实施例中，Σ-Δ调制器控制沿着锁相环路的反馈路径设置的脉冲吞咽分频器的值，以实现期望的噪声抑制水平。 在另一个实施例中，输入到锁相环中的参考信号被调制以实现噪声抑制。 在另一个实施例中，上述形式的调制被组合以实现期望的频移。 通过这些调制技术，频率发生器的信噪比可以显着提高，同时实现更快的锁定时间。

    FREQUENCY SYNTHESIZER USING TWO PHASE LOCKED LOOPS
    59.
    发明申请
    FREQUENCY SYNTHESIZER USING TWO PHASE LOCKED LOOPS 审中-公开
    频率合成器采用两相锁定环

    公开(公告)号：WO2008036389A2

    公开(公告)日：2008-03-27

    申请号：PCT/US2007020450

    申请日：2007-09-21

    Applicant: GCT SEMICONDUCTOR INC ,  PARK JOONBAE ,  LEE KYEONGHO ,  KOO YIDO ,  LEE JEONG-WOO

    Inventor： PARK JOONBAE ,  LEE KYEONGHO ,  KOO YIDO ,  LEE JEONG-WOO

    IPC: H04B1/06

    CPC classification number: H03L7/23 ,  H03L7/183 ,  H03L7/1976

    Abstract: The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and die second output frequency.

    Abstract translation: 该申请公开了涉及频率合成器的系统和方法实施例。 频率合成器的实施例可以具有低相位噪声和窄信道间隔。 频率合成器的实施例可以使用两个锁相环。 频率合成器的一个实施例可以包括用于输出具有参考频率的信号的参考频率振荡器，基于参考频率信号生成第一输出频率信号的整数N锁相环，分频N锁相环 基于参考频率信号和电路生成第二输出频率，以通过组合第一输出频率和第二输出频率来生成输出频率信号。

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