公开(公告)号：WO1995022217A1

公开(公告)日：1995-08-17

申请号：PCT/US1995001820

申请日：1995-02-09

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  KENNEDY, Michael ,  SCHILLACI, Onofrio

IPC: H04L25/02

CPC classification number: H04L25/0262 ,  H04Q2213/1307 ,  H04Q2213/13092 ,  H04Q2213/13096 ,  H04Q2213/1316 ,  H04Q2213/13166 ,  H04Q2213/13174 ,  H04Q2213/13199 ,  H04Q2213/13204 ,  H04Q2213/13213 ,  H04Q2213/13216 ,  H04Q2213/13332

Abstract: An autobaud dectection mechanism, installed as part of the communication control software of a serial communication device's microcontroller, enables the device to automatically determine the baud rate employed by a remote digital data communications device. Starting with a default baud rate, corresponding to the highest available baud rate, the mechanism steps through successively lower baud rates in the course of a search for the baud rate at which the remote device is transmitting. When an incoming call is received, respective bits of the received data are examined for the presence of transmission errors. If a transmission error is detected, the baud rate is stepped to the next lowest baud rate. If no error is detected, the received data bits are compared with a reference character. If the two compared data bit patterns match, the controller locks the baud rate at that baud setting for the remainder of the call. When the call is terminated, the baud rate reverts to its default setting. If the bit pattern comparison does not indicates a match, the baud rate is stepped to the next lowest baud rate. When the autobaud detection routine has stepped to a new baud rate entry, it initiates a prescribed time-out as a safeguard against the receiver becoming "out-of-sync" with a transmitter. Once, the lowest baud rate has been reached, the routine steps to the default setting and starts again.

Abstract translation: 作为串行通信设备的微控制器的通信控制软件的一部分安装的自动波特率检测机制使设备能够自动确定远程数字数据通信设备采用的波特率。 从与最高可用波特率相对应的默认波特率开始，该机制在搜索远程设备正在发送的波特率的过程中逐步降低波特率。 当接收到来电时，检查接收到的数据的各个比特是否存在传输错误。 如果检测到传输错误，则波特率步进到下一个较低的波特率。 如果没有检测到错误，则将接收的数据位与参考字符进行比较。 如果两个比较的数据位模式匹配，则控制器将在该波特率设置下锁定波特率以用于剩余的呼叫。 当呼叫终止时，波特率恢复为默认设置。 如果位模式比较不表示匹配，则波特率将步进到下一个较低的波特率。 当自动波特率检测程序进入新的波特率条目时，它启动一个规定的超时，作为防止接收机与发射机“不同步”的保护措施。 一旦达到最低的波特率，例程就会进入默认设置并重新开始。

公开(公告)号：WO1994025983A1

公开(公告)日：1994-11-10

申请号：PCT/US1994004628

申请日：1994-04-26

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  TEMPLE, Victor, A., K.

IPC: H01L23/051

CPC classification number: H01L29/7802 ,  H01L23/051 ,  H01L23/4824 ,  H01L24/06 ,  H01L29/4238 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor chip having a cellular topography and a method of packaging a cellular semiconductor chip includes plural interdigitated metal gate runners that overlie and contact selected gate electrodes on the chip surface, each of the gate runners having an integral widened area to enable a package carried gate electrode contact foil to be bonded thereto. The gate runner widened areas are relatively small and have little impact on chip active area. The plural gate runners have portions that underlie a package-carried power electrode contact foil and that are separated therefrom by a nonbondable, insulating layer. The gate runners may be deposited on the chip in the same step and from the same material as the power electrode. The portion of the power electrode on the chip surface that underlies the package-carried gate electrode contact foil is separated therefrom and available for use as active area of the chip. Package lid-to-chip alignment tolerances may be relaxed as they are not dictated by alignment of the lid-carried gate contact foil with the gate electrode on the chip.

Abstract translation: 具有细胞形貌的半导体芯片和封装蜂窝半导体芯片的方法包括覆盖并接触芯片表面上的选定栅电极的多个叉指金属栅极流道，每个栅极流道具有整体加宽的区域，以使得封装载体栅极 要接合的电极接触箔。 闸口加宽区域相对较小，对芯片活动区域影响不大。 多个栅极流道具有位于封装携带的电极接触箔的下方的部分，并且通过非粘结的绝缘层与其分离。 浇道浇道可以以相同的步骤和与电源电极相同的材料沉积在芯片上。 位于封装载体栅极电极接触箔下方的芯片表面上的功率电极的部分被分离并可用作芯片的有效区域。 封装盖对芯片对准公差可以被放宽，因为它们不是由盖带电栅极接触箔与芯片上的栅电极的对准所决定的。

公开(公告)号：WO1994020985A1

公开(公告)日：1994-09-15

申请号：PCT/US1994002569

申请日：1994-03-09

Applicant: HARRIS CORPORATION ,  SCHRANTZ, Gregory, A. ,  LINN, Jack, H. ,  BELCHER, Richard, W.

Inventor： HARRIS CORPORATION

IPC: H01L21/76

CPC classification number: H01L24/83 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76286 ,  H01L23/3732 ,  H01L24/29 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S438/973 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00014

Abstract: A semiconductor-on-insulator structure incorporating a layer of diamond material and method for preparing such. The structure comprises a layer containing diamond material and having a first surface. A layer of silicon nitride is formed on the first surface and a layer of semiconductor material is positioned over the silicon nitride layer. In one embodiment of the method there is provided a removable deposition surface. A layer of crystalline diamond material is formed on the deposition surface. A first surface of the diamond material is separated from the deposition surface. The structure is useful for formation of integrated circutis thereon.

Abstract translation: 包含金刚石材料层的绝缘体上半导体结构及其制备方法。 该结构包括含有金刚石材料并具有第一表面的层。 在第一表面上形成氮化硅层，并且半导体材料层位于氮化硅层上方。 在该方法的一个实施例中，提供了可移除的沉积表面。 在沉积表面上形成一层结晶金刚石材料。 金刚石材料的第一表面与沉积表面分离。 该结构对于在其上形成集成电路是有用的。

公开(公告)号：WO1994007261A1

公开(公告)日：1994-03-31

申请号：PCT/US1993008827

申请日：1993-09-17

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  CHERNE, Richard, D.

IPC: H01L21/336

CPC classification number: H01L29/66772 ,  H01L21/86 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78621

Abstract: The gain of a parasitic lateral bipolar device in a MOS SOI structure is substantially reduced so as to increase the differential between the snap-back sustaining voltage and the maximum recommended power supply voltage. Prior to insulated gate structure definition, very lightly doped source and drain regions are implanted so that they extend down to the underlying insulator layer. By very lightly doped is meant that the source and drain regions have a doping concentration that is within an order of magnitude of the doping concentration of the well portion of the semiconductor layer. Because the very lightly doped and physically deep source and drain regions are implanted in the absence of gate structure the implanted energy can be increased above the level that is normally employed to bottom out heavily doped regions, so that the reduced doping density will extend completely through the well layer to the underlying oxide. After the very lightly doped regions have been implanted, the implant mask is stripped and an insulated gate structure is formed atop the channel surface portion of the well layer between the source and drain regions. Using the insulated gate structure as a mask, off-axis, high angle implants of the same conductivity type as the source and drain regions are carried out to a first depth that only partially penetrates the depth of the deep source and drain implants. Very shallow high impurity concentration ohmic contact regions are then formed in surface portions of the first and second regions, and ohmic contact layers are formed on the conductive gate layer and the high impurity concentration ohmic contact regions.

Abstract translation: MOS SOI结构中的寄生横向双极器件的增益被显着地减小，从而增加了回跳维持电压和最大推荐电源电压之间的差。 在绝缘栅极结构定义之前，非常轻掺杂的源极和漏极区域被注入，使得它们向下延伸到下面的绝缘体层。 通过非常轻掺杂意味着源区和漏区具有的掺杂浓度在半导体层的阱部分的掺杂浓度的一个数量级内。 因为在不存在栅极结构的情况下注入非常轻的掺杂和物理深度的源极和漏极区域，所以注入的能量可以增加到高于通常用于底部重掺杂区域的电平，使得降低的掺杂密度将完全延伸通过 井层到底层氧化物。 在植入非常轻的掺杂区域之后，剥离注入掩模，并且在源极和漏极区域之间的阱层的沟道表面部分顶部形成绝缘栅极结构。 使用绝缘栅极结构作为掩模，与源极和漏极区域相同的导电类型的离轴，高角度植入被执行到仅部分地穿透深源和漏极植入物的深度的第一深度。 然后在第一和第二区域的表面部分中形成非常浅的高杂质浓度欧姆接触区域，并且在导电栅极层和高杂质浓度欧姆接触区域上形成欧姆接触层。

公开(公告)号：WO1993026041A1

公开(公告)日：1993-12-23

申请号：PCT/US1993005828

申请日：1993-06-17

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  BEASOM, James, Douglas ,  McLACHLAN, Craig, James

IPC: H01L21/76

CPC classification number: H01L21/76 ,  H01L21/2007 ,  H01L21/46 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76286 ,  Y10S148/012 ,  Y10S148/05 ,  Y10S438/938

Abstract: Warpage in a bonded wafer is limited by maintenance of a stress compensation layer on the backside of the bonded wafer during device fabrication processing. One embodiment applies a sacrificial polysilicon layer over a stress compensation silicon dioxide layer for bonded silicon wafers. The fabrication processing consumes the polysilicon layer but not the stress compensation silicon dioxide.

Abstract translation: 在器件制造处理期间，通过在接合晶片的背面上的应力补偿层的维持来限制粘合晶片中的翘曲。 一个实施例在用于接合硅晶片的应力补偿二氧化硅层上施加牺牲多晶硅层。 制造处理消耗多晶硅层，但不消耗应力补偿二氧化硅。

公开(公告)号：WO1993018519A1

公开(公告)日：1993-09-16

申请号：PCT/US1993002231

申请日：1993-03-03

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  PRESLAR, Donald, Ray

IPC: G11C11/40

CPC classification number: H01L27/115 ,  G11C16/0408 ,  H01L29/7886

Abstract: An EPROM cell comprises an MOS device including a floating gate electrode (44, 64) overlying, and ohmically insulated from, the channel region (26) of the MOS device, and a separate diode (18) including a p-n junction (54) having a substrate surface intercept (30). A floating gate electrode (64) overlies the diode p-n junction intercept (54) and is ohmically isolated therefrom by an intervening insulating layer. Writing of data into the floating gate electrode of the MOS device is achieved by causing a voltage breakdown across the diode p-n junction (54) and the flow of high energy electrons across the junction. A voltage is simultaneously applied to the diode gate electrode (64) thereby attracting some of the high energy electrons through the overlying insulating layer into the diode floating gate electrode. The diode gate electrode (64) is ohmically connected to the MOS floating gate electrode (44) on which some of the electrons are stored for affecting the turn-on, turn-off, characteristics of the MOS device.

Abstract translation: EPROM单元包括MOS器件，其包括覆盖MOS器件的沟道区域（26）并与欧姆绝缘的浮栅电极（44,64），以及包括pn结（54）的单独二极管（18），所述pn结（54）具有 衬底表面截距（30）。 浮栅电极（64）覆盖二极管p-n结截面（54），并通过中间绝缘层与其隔离。 通过在二极管p-n结（54）之间引起电压击穿和穿过该结的高能电子流，实现将数据写入MOS器件的浮置栅电极。 电压同时施加到二极管栅电极（64），从而将一些高能电子通过上覆绝缘层吸引到二极管浮栅中。 二极管栅极（64）欧姆连接到其上存储一些电子的MOS浮栅电极（44），以影响MOS器件的导通，关断特性。

公开(公告)号：WO1993017514A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001546

申请日：1993-02-19

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  PRENTICE, John, S.

IPC: H04M03/00

CPC classification number: H04M19/005 ,  H04M3/005 ,  Y10T307/74

Abstract: A subscriber line circuit for a telephone network having current controlled switches and current sources. Methods of making and using the components are also disclosed.

Abstract translation: 一种用于具有电流控制开关和电流源的电话网络的用户线电路。 还公开了制造和使用组件的方法。

公开(公告)号：WO1992017906A1

公开(公告)日：1992-10-15

申请号：PCT/US1992002350

申请日：1992-03-25

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  DEJONG, Glenn, A. ,  SCOTT, Gregory, J. ,  ITO, Akira

IPC: H01L29/08

公开(公告)号：WO1992007384A1

公开(公告)日：1992-04-30

申请号：PCT/US1991007544

申请日：1991-10-15

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  GROSSET, Mark, Allan ,  HSU, Chuan-Ding, Arthur

IPC: H01L29/06

CPC classification number: H01L27/0251 ,  H01L29/868

Abstract: A semiconductor protection circuit comprises a semiconductor substrate (2) of a first conductivity type; a first region (6) of the first conductivity type formed in the substrate at a surface thereof and having a relatively different degree of conductivity from the substrate; a region of a second conductivity type (8) formed in the first region (6) of the first conductivity type; and a second region (10) of the first conductivity type formed partly in each of the semiconductor substrate (2) and the first region (6) of the first conductivity type so as to bridge a junction therebetween.

公开(公告)号：WO1991018341A1

公开(公告)日：1991-11-28

申请号：PCT/US1991003374

申请日：1991-05-14

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  BURTON, Willie, Thomas, Jr. ,  MYERS, Brent, Arnold ,  WILES, William, Walter, Jr.

IPC: G06F03/05

CPC classification number: H03H11/04

Abstract: Impulse noise suppression upstream of digital processing circuitry contains a sample and hold (S/H) mechanism (24) which samples the input signal and stores a plurality of sequential samples representative of the amplitude of the input signal at successive times. The contents of the S/H are compared with an input signal sample (22) to determine whether there are abnormal amplitude variations which potentially constitute impulse noise. In one embodiment the comparison is referenced to the average magnitude (fig. 6) of the input signal. In another embodiment a cascaded arrangement (fig. 5) of S/H circuits (54-1-N) sample and store a plurality of sequential samples values. The contents of the last S/H circuit (54-N) are compared with the contents of each of selected other S/H circuits of the cascaded chain. A potential noise impulse sample is prevented from being coupled to downstream processing circuitry. Otherwise it is coupled through a downstream lowpass filter for subsequent signal analysis.