公开(公告)号：WO1993013474A1

公开(公告)日：1993-07-08

申请号：PCT/DE1992001051

申请日：1992-12-16

Applicant: ROBERT BOSCH GMBH ,  MATTES, Bernhard ,  SCHUMACHER, Hartmut ,  CRISPIN, Norbert ,  NITSCHKE, Werner ,  DROBNY, Wolfgang ,  KARL, Otto

Inventor： ROBERT BOSCH GMBH

IPC: G06F03/05

CPC classification number: B60R16/0315 ,  G06F1/22 ,  G06F3/05 ,  G08C15/06

Abstract: The invention concerns an electronic control device for, in particular, motor-vehicle applications and with a single-chip circuit (2), the device comprising a resistor network (R1, R2, R3, R4) connected to digital output terminals (01, 02). This makes multiple use of at least one input terminal (A1, A8) of the circuit (2) possible.

Abstract translation: 本发明涉及一种用于特别是机动车辆应用和单芯片电路（2）的电子控制装置，该装置包括连接到数字输出端子（01）的电阻网络（R1，R2，R3，R4） 02）。 这使得可以多次使用电路（2）的至少一个输入端子（A1，A8）。

公开(公告)号：WO1987003114A1

公开(公告)日：1987-05-21

申请号：PCT/GB1986000689

申请日：1986-11-07

Applicant: BURR-BROWN LIMITED ,  HARDIE, Ian

Inventor： BURR-BROWN LIMITED

IPC: G06F03/05

CPC classification number: G06F3/05

Abstract: An interface unit between analog signals from a device being monitored and a digital signal data bus includes a multiplexer unit, a sample and hold amplifier, an analog to digital converter, a buffer memory unit, and control circuits. The control circuits are responsive to signals from a central processing unit and can control the operating parameters of the interface unit, including a software programmable clock. The control circuits can also generate interrupt signals.

Abstract translation: 来自被监视装置的模拟信号和数字信号数据总线之间的接口单元包括多路复用器单元，采样和保持放大器，模数转换器，缓冲存储器单元和控制电路。 控制电路响应于来自中央处理单元的信号，并且可以控制接口单元的操作参数，包括软件可编程时钟。 控制电路也可以产生中断信号。

公开(公告)号：WO1991018341A1

公开(公告)日：1991-11-28

申请号：PCT/US1991003374

申请日：1991-05-14

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  BURTON, Willie, Thomas, Jr. ,  MYERS, Brent, Arnold ,  WILES, William, Walter, Jr.

IPC: G06F03/05

CPC classification number: H03H11/04

Abstract: Impulse noise suppression upstream of digital processing circuitry contains a sample and hold (S/H) mechanism (24) which samples the input signal and stores a plurality of sequential samples representative of the amplitude of the input signal at successive times. The contents of the S/H are compared with an input signal sample (22) to determine whether there are abnormal amplitude variations which potentially constitute impulse noise. In one embodiment the comparison is referenced to the average magnitude (fig. 6) of the input signal. In another embodiment a cascaded arrangement (fig. 5) of S/H circuits (54-1-N) sample and store a plurality of sequential samples values. The contents of the last S/H circuit (54-N) are compared with the contents of each of selected other S/H circuits of the cascaded chain. A potential noise impulse sample is prevented from being coupled to downstream processing circuitry. Otherwise it is coupled through a downstream lowpass filter for subsequent signal analysis.

公开(公告)号：EP0105086A3

公开(公告)日：1987-07-22

申请号：EP83105725

申请日：1983-06-10

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Bonivich, Paul Edward

IPC: H03K13/02 ,  G06F03/05

CPC classification number: G05B19/4142 ,  G05B19/351 ,  G05B2219/37297 ,  G05B2219/41105 ,  H03M1/308 ,  H03M1/485

Abstract: An interfacing system for selectably interfacing signals to a computer, or other control apparatus such as a numerical control system, from either of alternative transducers (12, 14) which provide position indicative signals differing in format. A system according to the invention is useful for interfacing signals to a control system from either a resolver (14) or an encoder (12) and includes a digital counter (22) whose output count, irrespective of the transducer type, is indicative of the monitored object's position. A data latch (48) connected between the control or receiving instrumentation and the counter (22) holds a count at an appropriate time and then provides a transfer of the position indicative count to the receiving instrumentation. Circuitry (28) is included for automatically causing the counter to function as a reversing counter or as a reference counter, depending on the type of transducer signals to be interfaced.

公开(公告)号：EP0084247A3

公开(公告)日：1984-05-30

申请号：EP82306835

申请日：1982-12-21

Applicant: FUJITSU LIMITED

Inventor： Murakami, Joji c/o FUJITSU LIMITED

IPC: G06F01/00 ,  G06F03/05

Abstract: Operation mode setting circuitry, for a microprocessor operable in a plurality of operation modes, has a single input pin (2) through which an analog voltages the level of which serves for designating one of the operation modes, is applied to an analog-to-digital converter circuit (6) which is built into the microprocessor. The output digital signal from the analog-to-digital converter circuit (6) is decoded by a decoder (16), and the microprocessor is set at the designated operation mode in response to the decoded output signal.

公开(公告)号：EP0072342A3

公开(公告)日：1985-04-17

申请号：EP82730103

申请日：1982-08-03

Applicant: FUJI ELECTRIC CO. LTD.

Inventor： Yasuhara, Takeshi, Dipl.-Ing. ,  Nabeta, Eiichi, Dipl.-Ing.

IPC: G01D01/00 ,  G06F03/05

CPC classification number: G01L9/12 ,  G01D5/248 ,  G01R19/25 ,  G01R19/252 ,  G01R19/255

Abstract: Eine Messeinrichtung bestimmt eine physikalische Grösse nach ihrer Erfassung durch Umwandlung in eine digitale Grösse, die vorbestimmten Rechenoperationen unterzogen wird. Eine übergeordnete Prozessoreinheit gibt einen Steuerbefehl zur Inbetriebsetzung der Messeinrichtung sowie ein Setzsignal ab, durch das eine bistabile Schaltung (FF) setzbar ist. Sind die vorbestimmten Rechenoperationen in einer digitalen Prozessor einheit (7) der Messeinheit durchgeführt, so wird hierdurch die bistabile Schaltung (FF) zurückgestellt. Eine Verzögerungs schaltung (R
SB , C
SB ) verzögert eine Ausgangsgrösse der bistabi len Schaltung (FF) um eine vorbestimmte Zeit und sorgt für die Stillsetzung der digitalen Prozessoreinheit (7) nach einer für ihre Überführung in einen Bereitschaftszustand erforderlichen Zeit. Die Messeinrichtung ist insbesondere zur Messung eines Druk kes oder eines Differenzdruckes geeignet.

公开(公告)号：EP0042350A3

公开(公告)日：1983-01-19

申请号：EP81630043

申请日：1981-06-11

Applicant: UNITED TECHNOLOGIES CORPORATION

Inventor： Stack, Timothy Francis ,  Shoemaker, George Thomas

IPC: G06F03/05 ,  G08C09/04 ,  G06F15/20

CPC classification number: G06F3/05 ,  H03M1/124

Abstract: universal analog signal interface includes a pair of signal conditioning circuits, each responsive to one of a pair of analog signals presented between two inputs of each for providing corresponding pairs of output signal manifestations representative of the magnitude and the phase of the pair of signals received; the analog interface further including signal conversion circuitry responsive to each of the pairs of signal manifestations of magnitude and phase for providing a digital signal representative of the ratio of the smaller magnitude signal manifestations divided by the larger magnitude signal manifestation and for providing digital signals representative of each of the phase signal manifestations.

公开(公告)号：WO1992020025A1

公开(公告)日：1992-11-12

申请号：PCT/DE1992000279

申请日：1992-04-03

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  SEZI, Tevfik

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: G06F03/05

CPC classification number: H03M1/0658 ,  G06F3/05 ,  G08C15/06 ,  H03M1/1225 ,  H04J3/047

Abstract: The invention concerns a circuit arrangement for converting a plurality of analog electrical measurement signals to corresponding digital signals. To obtain such a circuit with a fairly simple structure, antialiasing filters (11) on the input side are connected on the output side to at least two multiplexers (14, 20; 26, 27) associated with at least two scanning-holding circuits (15, 21; 28, 29). At least two analog-digital converters (16, 22; 30, 31) are connected on the input side to the output of a scanning-holding circuit (15, 21; 28, 29). An evaluation device (18) is arranged after the at least two analog-digital converters (16, 22; 30, 31) and determines, in an evaluation interval (O - T1), several digital values corresponding to scanning values of an electric signal (M1, M2) and averages them to produce the corresponding digital signal. The at least two multiplexers (14, 20, 26, 27) are connected to a control device (24) which controls said multiplexers so that the outputs of the antialiasing filters (11) are connected consecutively and in sequence via one multiplexer (e.g., 14) and, at the same time, consecutively and in reversed sequence via the second multiplexer (e.g., 20) to the scanning holding circuit (e.g., 15, 21).

公开(公告)号：WO1981001759A1

公开(公告)日：1981-06-25

申请号：PCT/JP1980000301

申请日：1980-12-08

Applicant: MITSUBISHI DENKI KK ,  GOUDA T ,  HATATA M

Inventor： MITSUBISHI DENKI KK

IPC: G06F03/05

CPC classification number: G06F11/0751 ,  G06F3/05

Abstract: An abnormal signal detecting device, comprising a signal sampling and conversion circuit for sampling a predetermined number of data points along an analog signal and generating digital sampled data signals representative thereof; a memory circuit, connected to the signal sampling and conversion circuit, for storing the digital sampled data; and a consistency detecting circuit, connected to the memory circuit, for comparing at least three consecutive digital sampled data signals and generating an output representing an abnormal condition whenever at least three consecutive digital sampled data signals are the same.

Abstract translation: 一种异常信号检测装置，包括信号采样和转换电路，用于沿着模拟信号对预定数量的数据点进行采样，并产生代表其的数字采样数据信号; 连接到信号采样和转换电路的存储电路，用于存储数字采样数据; 以及连接到存储器电路的一致性检测电路，用于比较至少三个连续的数字采样数据信号，并且每当至少三个连续的数字采样数据信号相同时产生表示异常状况的输出。