公开(公告)号：JP2009227276A

公开(公告)日：2009-10-08

申请号：JP2009120107

申请日：2009-05-18

Applicant: Hitachi Ltd ,  株式会社日立製作所

Inventor： YOSHIMURA KENTARO ,  SAKURAI KOHEI ,  KANEKAWA NOBUYASU ,  MORITA YUICHIRO ,  TAKAHASHI YOSHIAKI ,  KUROSAWA KENICHI ,  MINOWA TOSHIMICHI ,  HOSHINO MASATOSHI ,  NAKATSUKA YASUHIRO ,  SHIMAMURA KOTARO ,  TSUNETOMI KUNIHIKO ,  SASAKI SHOJI

IPC: B60T8/17 ,  B60T8/1755 ,  B60T8/96 ,  B60T17/18 ,  B60W10/00 ,  B60W10/04 ,  B60W10/06 ,  B60W10/10 ,  B60W10/18 ,  B60W10/188 ,  B60W10/20 ,  B60W30/00 ,  B60W50/02 ,  B62D6/00 ,  B62D7/14 ,  B62D103/00 ,  B62D111/00 ,  B62D113/00 ,  B62D137/00

CPC classification number: Y02T10/6286 ,  Y02T10/7275

Abstract: PROBLEM TO BE SOLVED: To provide a vehicle controller for securing high reliability, real time property and scalability at low cost, with a simple constitution of an ECU, by backing up an error in the whole system without unnecessarily increasing redundancy of each controller. SOLUTION: In this vehicle controller, a sensor controller 2 capturing a sensor signal indicating a state quantity of a vehicle and a control variable of a driver, a command controller for generating a control target value based on the sensor signal, and an actuator controller 3 for operating an actuator 5 for receiving the control target value to control a vehicle are connected via a network. The actuator controller 3 has a control target value generating means for generating the control target value based on a sensor value on the network received by the actuator controller 3, when an error occurs in the control target value generated by the command controller, and controls the actuator 5 by the control target value. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种以低成本确保高可靠性，实时性和可扩展性的车辆控制器，具有简单的ECU结构，通过在整个系统中备份错误，而不必增加每个系统的冗余 控制器。 解决方案：在该车辆控制器中，传感器控制器2捕获指示车辆的状态量的传感器信号和驾驶员的控制变量，用于基于传感器信号生成控制目标值的命令控制器，以及 用于操作用于接收控制目标值以控制车辆的致动器5的致动器控制器3通过网络连接。 执行器控制器3具有控制目标值产生装置，当由指令控制器产生的控制目标值发生错误时，基于由致动器控制器3接收到的网络上的传感器值来生成控制目标值，并且控制 执行器5由控制目标值。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007126127A

公开(公告)日：2007-05-24

申请号：JP2006260628

申请日：2006-09-26

Applicant: Hitachi Ltd ,  株式会社日立製作所

Inventor： SAKURAI KOHEI ,  MATSUBARA MASAHIRO ,  HOSHINO MASATOSHI ,  MORITA YUICHIRO ,  TAKAHASHI YOSHIAKI ,  KUROSAWA KENICHI

IPC: B60R16/02 ,  B60R16/023 ,  G08G1/09 ,  G08G1/16

CPC classification number: B60W50/0205

Abstract: PROBLEM TO BE SOLVED: To provide a vehicle control system using a number of ECUs which perform coordinating operation via a network while inexpensively and accurately specifying a fault node in the network. SOLUTION: Each node is composed of an in-network node state determining means, an own-node state determination result transmitting means and an other-node state determination result receiving means, and a fault node specifying means. By exchanging a result determined by the in-network node state determining means with the other node. the fault node is specified. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用多个ECU执行协调操作的ECU的车辆控制系统，同时廉价且准确地指定网络中的故障节点。 解决方案：每个节点由网络内节点状态确定装置，自身节点状态确定结果发送装置和另一个节点状态确定结果接收装置以及故障节点指定装置组成。 通过将由网络内节点状态确定装置确定的结果与另一个节点进行交换。 指定故障节点。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006344244A

公开(公告)日：2006-12-21

申请号：JP2006238436

申请日：2006-09-04

Applicant: HITACHI LTD

Inventor： ARITA YUTAKA ,  NAKAMIGAWA TETSUAKI ,  KUROSAWA KENICHI ,  OKAMOTO TADASHI ,  MIYAZAKI YOSHIHIRO

IPC: G05B23/02

Abstract: PROBLEM TO BE SOLVED: To reduce the amount of data transfer between a controller and a controlled apparatus. SOLUTION: A data transfer system is composed of a memory which stores state data that indicates at least the state of a control target and control data to control the control target, a computer which acquires control data for the control target based on the state data stored in the memory, a memory controller which reads out the state data from the memory and writes the data acquired by the computer into the read state data to store it into the memory, and a data transfer apparatus which reads out the data rewritten by the memory controller from the memory to transmit it. COPYRIGHT: (C)2007,JPO&INPIT

公开(公告)号：JP2004139364A

公开(公告)日：2004-05-13

申请号：JP2002303701

申请日：2002-10-18

Applicant: Hitachi Ltd ,  株式会社日立製作所

Inventor： YAMADA TSUTOMU ,  NAKAMIGAWA TETSUAKI ,  KUROSAWA KENICHI ,  MASUI KOJI ,  OGURA MAKOTO

IPC: G06F13/36

Abstract: PROBLEM TO BE SOLVED: To solve the problem that the degree of freedom of change is low even when a bus system is changed in a range where the meaning of a signal line such as an address or data is not changed or the bus system is newly added in order to improve transfer performance since the timing to switch the bus system is statically decided on start-up. SOLUTION: This bus system is provided with a sequencer discriminating part and a signal converting part, and a signal to be transferred to a sequencer executing part is dynamically constituted according to the start signal of a bus. This bus system makes it possible to flexibly decide and add a new bus system in a bus system where a conventional bus system exists, and allows a bus device corresponding only to the conventional bus system to coexist without being affected. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2001127467A

公开(公告)日：2001-05-11

申请号：JP30350399

申请日：1999-10-26

Applicant: HITACHI LTD

Inventor： YAMAMOTO MASAYUKI ,  TAKEWA HIDEHITO ,  KUROSAWA KENICHI

IPC: G06F1/18 ,  H05K1/02 ,  H05K7/14

Abstract: PROBLEM TO BE SOLVED: To provide a printed board which can be applied to both industrial personal computers and panel computers, thus saving time and cost for designing. SOLUTION: On a printed board 1, mounted with expansion board connectors and expansion card slots containing common signal line groups 4, 5 and 6, the line groups 4, 5, and 6 are arranged in an L-form and foot prints 3 and 10 for expansion card slots are arranged in both vertical and horizontal directions, so that the mounting positions of expansion card slots can be changed. Accordingly, the printed board 1 is made so that it can be applied to both industrial computers and panel computers.

公开(公告)号：JP2000330929A

公开(公告)日：2000-11-30

申请号：JP14459399

申请日：1999-05-25

Applicant: HITACHI LTD

Inventor： ISHIKURA HIDEJI ,  KUROSAWA KENICHI ,  TAKEWA HIDEHITO ,  OGURA MAKOTO

IPC: G06F13/28

Abstract: PROBLEM TO BE SOLVED: To improve the use efficiency of a bus by optimizing burst transfer size by a system which is variable in the maximum burst transfer quantity of a reception side. SOLUTION: When the number of pieces of transmit data stored in a memory 9 from an input/output device 3 exceeds burst transmission size (TXDC), an input/output controller 1 as an initiator sets the TXDC in a transmission counter 15 when a transmission is requested and actuates a PCI controller 11 to transfer the data to a target-side CPU 2 up to the transmission counter value successively by the data width of the PCI bus 5 at a time. To receiving a transmission, data are transferred similarly. If a disconnection request is made by the target side in burst transfer, the data transfer is interrupted, so the initiator size makes a restart. An MPU 9 monitors a PIC monitor 12 which counts the frequency of actuation and the frequency of disconnection separated by the transmission and reception and periodically repeats an updating processing for subtracting the bus data width from the TXDC (or RXDC) until the generation frequency of disconnection becomes a threshold less than the frequency of actuation.

公开(公告)号：JP2000013462A

公开(公告)日：2000-01-14

申请号：JP17434198

申请日：1998-06-22

Applicant: HITACHI LTD

Inventor： ISHIKURA HIDEJI ,  KUROSAWA KENICHI ,  OKURA TAKANORI ,  YAMADA TSUTOMU

IPC: H04L29/06 ,  H04L12/40

Abstract: PROBLEM TO BE SOLVED: To provide cyclic transfer which fully utilizes the performance of a transmission line by performing an operation by switching plural communication protocols that are completely different on the same transmission line. SOLUTION: This communication controller 8 switches the connection of a system bus 9 and a cyclic transfer data processing circuit 7 by means of a bus changeover switch 13. The controller 8 is a controller which performs communication protocol control conforming to IEEE802.3 and when it is connected to the bus 9, it performs data transmission and reception with many devices with an IEEE802.3 communication protocol in the control of an MPU 10 according to a control program stored in a memory 6 via a transmission line 1. Also, when it is connected to the circuit 7, it transmits frame data of a self-node which is transmitted from the circuit 7 in an IEEE802.3 physical specification from the line 1 by the control of the circuit 7.

公开(公告)号：JPH11338833A

公开(公告)日：1999-12-10

申请号：JP14078898

申请日：1998-05-22

Applicant: HITACHI LTD

Inventor： TAKEWA HIDEHITO ,  OGURA MAKOTO ,  ISHIKURA HIDEJI ,  MATSUDA KOJI ,  KUROSAWA KENICHI ,  TAKAHASHI YOSHIAKI

IPC: G06F12/14 ,  G06F9/46 ,  G06F9/48 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To improve independence between processors in the case of an interruption notice and to make compatible a common program in initializing processing and independence between processors. SOLUTION: Concerning the multiprocessor type controller equipped with plural processors 101-102 and a shared memory 112, this controller is provided with a boundary register for holding the boundaries of areas dividing the shared memory 112 for each processor, comparator for comparing the access address of the shared memory 112 with the boundary register, memory control part 107 for limiting the access of the processor based on the compared result of the comparator, interruption control part 106 for reporting interruption according to a mask register for masking an interruption factor for each processor, and identification register for returning a different value through the processor at the reading source. Thus, the independence of processors is improved by the selective notice of interruption while protecting the areas of the shared memory 112 in ordinary processing and the processing when started up can be made common by the identification register.

公开(公告)号：JPH11134251A

公开(公告)日：1999-05-21

申请号：JP29236097

申请日：1997-10-24

Applicant: HITACHI LTD

Inventor： OGURA MAKOTO ,  KUROSAWA KENICHI ,  OKAMOTO TADASHI

IPC: G06F12/06

Abstract: PROBLEM TO BE SOLVED: To provide a sequence controller capable of updating by latest data even in the case that the processing cycle of a sequence processing is short in the asynchronous parallel processings of an input/output processing and the sequence processing. SOLUTION: A dual port memory accessible from an input/output unit 9 and a CPU unit 1 is provided for plural banks 5-7 and a CPU 1 confirms the transfer completion of the input/output unit 9 at the end of the sequence processing and instructs bank changeover to a memory management unit 16. The memory management unit 16 is provided with a register 15 or the like for indicating the transfer completion by the input/output unit 9 and the register 4 provided with bank changeover logic and switches the addresses of the dual port memory accessed by the CPU unit 1 and the input/output unit 9 when a transfer completion flag is set and the bank changeover is instructed. Thus, even in the case that an input/output processing cycle is longer than a sequence processing cycle, the processing cycle of the latter is guaranteed to be long practically.

公开(公告)号：JPH1141178A

公开(公告)日：1999-02-12

申请号：JP19699297

申请日：1997-07-23

Applicant: HITACHI LTD

Inventor： ARITA YUTAKA ,  NAKAMIGAWA TETSUAKI ,  KUROSAWA KENICHI ,  FUKUMARU HIROAKI ,  OGAWA HISAO

IPC: H04B10/00 ,  H04B10/07 ,  H04B10/27 ,  H04L12/28 ,  H04L12/46 ,  H04B10/20 ,  H04B10/08 ,  H04B10/24

Abstract: PROBLEM TO BE SOLVED: To improve a noise proofing property by partial optical communication in a network by matching driving states of two electric buses connected by an optical fiber with each other. SOLUTION: A bus 20a to connect nodes 30a, 30b is connected with a bus 20b to connect nodes 30c, 30d with optical bus bridge devices 10a, 10b by the optical fiber 50. ON states of the buses 20 (20a, 20b) are observed in a stand-by mode when the bus 20 is not driven by the optical bus bridge devices 10 (10a, 10b). When the bus 20a is changed to the ON state by being driven by the node 30a, the stand-by mode is transferred to an optical output mode and light is outputted from a photoelectric transducer 13a to the optical fiber 50. When the light outputted from the optical fiber 50 is received, the optical bus bridge device 10b is transferred from the stand-by mode to the bus drive mode and the state of the bus 20b is made coincide with that of the bus 20a by performing electric output from a bus driver circuit 11b by the optical bus bridge device 10b. The driving states of the buses 20a, 20b are fetched by the nodes 30b, 30c, 30d.