公开(公告)号：DE102004004785A1

公开(公告)日：2005-08-25

申请号：DE102004004785

申请日：2004-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: G11C5/02 ,  G11C5/14 ,  G11C11/34

Abstract: A semi-conductor component ( 1 ), in particular a memory component, with at least one voltage booster, which makes available an appropriate boosted voltage (VPP, VLL), and which is installed in a corresponding voltage booster area ( 101 a) of the semi-conductor component ( 1 ), whereby the voltage booster area ( 101 a) essentially extends parallel to several devices ( 9 a , 8 a , 8 c), which are to be provided with the boosted voltage (VPP, VLL), in particular essentially parallel to the lines, for instance word lines ( 12 a , 13 a , 13 b , 13 c) controlled by the devices ( 9 a , 8 a , 8 c).

公开(公告)号：DE102004004091A1

公开(公告)日：2005-08-25

申请号：DE102004004091

申请日：2004-01-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  HEYNE PATRICK ,  MINZONI ALESSANDRO ,  RAO RAJASHEKHAR ,  SZCZYPINSKI KAZIMIERZ

IPC: G06F1/10 ,  G11C7/22 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/135 ,  H03L7/081 ,  H03L7/087 ,  H03K5/15

Abstract: The invention involves a clock pulse synchronization process as well as a device ( 1, 101 ) to be used in the synchronization of clock pulses (CLK), containing a first delay apparatus ( 2 a) with variably controllable delay period (t var ), in which a clock pulse (CLK) or a signal derived from it, has a variably controllable delay period (t var ) imposed on it and is then emitted as a delayed signal (FBA), characterized in that in addition to the first delay apparatus ( 2 a) with variably controllable delay period (t var ), a second delay apparatus ( 2 b) with variably controllable delay period (t var ) is provided.

公开(公告)号：DE10329378B3

公开(公告)日：2005-02-10

申请号：DE10329378

申请日：2003-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  SCHNEIDER HELMUT

IPC: G11C7/12 ,  G11C11/406 ,  G11C11/4094

Abstract: The memory has a memory sub-unit in provided by a memory cell in which a dataword is stored and which is coupled to a bit line (6) and an associated pre-charge/equalize circuit (32,14), switched on and off by a control circuit. The pre-charge/equalize circuit is switched on for pre-charging the bit line in the normal memory cell refreshing mode by a control signal with a first voltage level and is switched on for pre-charging the bit line during a normal memory cell accessing mode by a control signal with a second voltage level. An independent claim for a battery-operated device with a semiconductor memory is also included.

公开(公告)号：DE69819606T2

公开(公告)日：2004-08-19

申请号：DE69819606

申请日：1998-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KAWASAKI KK

Inventor： BROX MARTIN ,  FREIMUTH FRANZ ,  KILLIAN MIKE ,  MIYAWAKI NAOKAZU ,  SCHAFFROTH THILO

IPC: G11C11/41 ,  G11C5/14 ,  G11C7/20 ,  G11C7/22 ,  G11C11/401 ,  G11C7/00

Abstract: A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

公开(公告)号：DE10260602B3

公开(公告)日：2004-08-12

申请号：DE10260602

申请日：2002-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: G11C7/06 ,  G11C11/4091

Abstract: The sense amplifier has a cross-coupled switching device (101) connected between the complementary bit lines (107,108) for the bit line signals (103,104), provided with 2 series transistor pairs (201,202; 105,106), cross-coupled to the bit lines at their gates and 2 further transistors (205,206), respectively connected in series with the transistors of the first transistor pair and receiving a switching signal (207) at their gates. A holding device (102) is connected across the bit lines for holding the switched signal level of the bit line signals applied to the bit lines. An independent claim for a method for detection and amplification of bit line signals is also included.

公开(公告)号：DE10110273C2

公开(公告)日：2003-04-24

申请号：DE10110273

申请日：2001-03-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTENSCHLAGER RAINER ,  BROX MARTIN ,  KEYSERLINGK ALBERT GRAF VON

IPC: G05F1/46 ,  G05F1/10 ,  G05F3/16

Abstract: A voltage generator for producing an internal supply voltage has a standby voltage generator and a voltage generator for normal operation that are controlled in common by a reference voltage. In addition, a comparator stage is provided whose switching threshold is set lower than the reference voltage by using a voltage divider that is connected to the reference voltage. The additional comparator stage thus activates the voltage generator for normal operation when the internally produced voltage falls below its switching threshold so that the internal supply voltage is stabilized.