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    SELECT-FREE ACCESS TYPE SEMICONDUCTOR MEMORY COMPRISING BUS SYSTEM ORIENTED IN TWO PLANES
    1.
    发明专利
    SELECT-FREE ACCESS TYPE SEMICONDUCTOR MEMORY COMPRISING BUS SYSTEM ORIENTED IN TWO PLANES 失效

    公开(公告)号：JP2000339990A

    公开(公告)日：2000-12-08

    申请号：JP2000115370

    申请日：2000-04-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN ,  PFEFFERL KARL-PETER

    IPC: G06F12/16 ,  G06F11/20 ,  G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To allow a plurality of redundant data lines to be flexibly associated with different groups by allowing a bus line on a first plane to be connected to all of input/output lines and all of data lines and allowing a plurality of independent partial buses on a second plane to be connected to data lines in at least two groups and an input/output line of each one group. SOLUTION: Data lines MDQii, of groups U1 to U8 are respectively connectable to IO lines RWDii of groups IO1 to IO4 via bus systems on two planes. All of bus lines Ai on a first plane A are connectable to all of data lines MDQ11, to MDQ88, redundant lines MDQ1R to MDQ8R, and IO lines RWD11 to RWD48. Bus lines Bi1 to Bi8 on a second plane composed of partial buses B1 to B4 are respectively connectable to two groups of the data lines MDQi1 to MDQi8, the redundant line MDQR, and one group of the IO lines RWDi1 to RWDi8.

    4.
    发明专利
    未知

    公开(公告)号：DE10333280B4

    公开(公告)日：2007-10-25

    申请号：DE10333280

    申请日：2003-07-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN

    IPC: G11C8/18 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    Abstract: The invention relates to a semi-conductor memory component and process for operating a semi-conductor memory component, including activating the memory cells of a memory cell array, when one or several memory cell(s) included in the first set of memory cells need(s) to be accessed, accessing the corresponding memory cell or memory cells, deactivating the memory cells contained in a first set of memory cells, when one or several further memory cells that are not included in the first set of memory cells need(s) to be accessed, and prematurely deactivating the memory cells included in the first set of memory cells, when a predetermined time period or number of pulses after one or several memory cells included in the first set of memory cells have last been accessed first no further accessing of one or several of the memory cells included in the first set of memory cells takes place.

    8.
    发明专利
    未知

    公开(公告)号：DE10261409B4

    公开(公告)日：2006-05-11

    申请号：DE10261409

    申请日：2002-12-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BROX MARTIN ,  MINZONI ALESSANDRO

    IPC: H03L7/081 ,  H03K5/00 ,  H03K5/15

    Abstract: The delay locked loop includes an additional delay element (102) connected in series with a first delay element (101). A frequency detector unit (110) detects the frequency of the input signal (103). The second delay element is adjustable based on the detected frequency of the input signal. Independent claims are included for a frequency detector unit and a method of providing clock signals in circuit units.

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