公开(公告)号：DE10034003A1

公开(公告)日：2002-01-24

申请号：DE10034003

申请日：2000-07-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108

Abstract: Trench capacitor comprises: trench (2) formed in semiconductor substrate (1); conducting capacitor plates (60, 80); a dielectric layer (70) as capacitor dielectric applied by atomic layer deposition, atomic layer chemical vapor deposition or chemical vapor deposition between the plates; insulating collar (5'') in an upper region of trench; and an optional conducting filler material in the trench. Preferred Features: The first plate is a region of high doping in the substrate in the lower region of the trench and the second plate is the conducting filler material. The dielectric layer is made of alumina (Al2O3), tantalum pentoxide (Ta2O5), zirconia (ZrO2), hafnium oxide (HfO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), aluminum - tantalum oxygen (Al-Ta-O), aluminum - zirconium - oxygen (Al-Zr-O), aluminum - hafnium - oxygen (Al-Hf-O), aluminum - lanthanum - oxygen (Al-La-O), aluminum - titanium oxygen (Al-Ti-O), zirconium yttrium - oxygen (Zr-Y-O), zirconium - silicon - oxygen (Zr-Si-O), hafnium - silicon - oxygen (Hf-Si-O), silicon - oxygen - nitrogen (Si-O-N), tantalum - oxygen - nitrogen (Ta-O-N), gadolinium oxide (Gd2O3), tin oxide (SnO3), lanthanum - silicon - oxygen (La-Si-O), titanium -silicon -oxygen (Ti-Si-O), lanthanum aluminate (LaAlO3), zirconium titanate (ZrTiO4), (zirconium, tin) titanate ((Zr, Sn)TiO4), strontium zirconate (SrZrO4), lanthanum aluminate (LaAlO4) or barium zirconate (BaZrO3).

公开(公告)号：DE102012217471A1

公开(公告)日：2014-01-23

申请号：DE102012217471

申请日：2012-09-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOLLER ADOLF ,  LESCHIK GERHARD ,  MACKH GUNTHER ,  SEIDL HARALD

IPC: H01L21/822

Abstract: Ein Chip umfasst eine dielektrische Schicht und eine Füllstruktur in der dielektrischen Schicht, wobei sich die Füllstruktur entlang einer Vereinzelungskante des Chips erstreckt, wobei die Füllstruktur an die Vereinzelungskante anstößt.

公开(公告)号：DE102006026949A1

公开(公告)日：2007-12-13

申请号：DE102006026949

申请日：2006-06-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD

IPC: H01L27/24 ,  H01L27/10

Abstract: The component (1) has a nano wire transistor (4) or nano tube- or nano fiber-access-transistor, having a transistor-gate-area , which is a part of a word-line. A contact surface between the nano wire-or nano tube or a nano fiber-access-transistor and a switching active material (2) of the component exhibit a specific width and/or the length and/or a diameter. The active material directly contacts to a nano wire or a nano tube or nano fiber of the transistor, and a capacitive unit is provided for storing of data. An independent claim is also included for a method for manufacturing a memory-component.

公开(公告)号：DE102005054931B3

公开(公告)日：2007-07-26

申请号：DE102005054931

申请日：2005-11-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD

IPC: H01L27/24

Abstract: The method involves producing two slat shaped spacers, where former slat shaped shaper is electrically connected with phase change material, and later slat shaped spacer is produced on the former slat shaped shaper. The former slat shaped shaper crosses later slat shaped spacer within range over phase change material surface. The material layer is removed in such a manner, that aggregation from material remains on edge of block in order to form the later slat shaped spacer.

公开(公告)号：DE102005060723A1

公开(公告)日：2007-06-28

申请号：DE102005060723

申请日：2005-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ULRICH ,  SEIDL HARALD ,  KREUPL FRANZ

IPC: B82B1/00 ,  B82B3/00 ,  G11C11/24 ,  H01L21/8242 ,  H01L27/108

Abstract: Arrangement has two freestanding structures that are superimposed on a substrate, where one structure is arranged at a distance to another structure. Nano-support units (103) are provided between the structures for supporting the structures, where the support units are designed as electrically insulating nano-wires and/or electrically insulating nano tubes. A set of electronic components is integrated into the substrate that is manufactured from silicon and/or silicon oxide. An independent claim is also included for a method for manufacturing a nano-arrangement.

公开(公告)号：DE102005051973B3

公开(公告)日：2007-06-28

申请号：DE102005051973

申请日：2005-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ULRICH ,  KREUPL FRANZ

IPC: H01L21/283 ,  G11C5/06 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：DE102004031111B4

公开(公告)日：2007-03-01

申请号：DE102004031111

申请日：2004-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD

IPC: H01L21/336 ,  G03F7/00 ,  G03F7/16 ,  H01L21/283 ,  H01L21/308

公开(公告)号：DE102005008478B3

公开(公告)日：2006-10-26

申请号：DE102005008478

申请日：2005-02-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ULRICH

IPC: G03F1/08 ,  G03F1/14 ,  G03F7/20 ,  H01L21/00

Abstract: The method involves preparing substrate (1), forming first auxiliary layer and then second auxiliary layer structure (3,4). The first auxiliary layer is anisotropically etched using the auxiliary structure as a mask to form an anisotropic structured first auxiliary layer structure. This is reverse isotropically etched to remove sections and form an isotropically structured first auxiliary structure. A mask is formed over the sections. This is anisotropically etched to the substrate to form sublithographic structure (5A). Auxiliary structures are removed to reveal the sublithographic structure.

公开(公告)号：DE102005014645A1

公开(公告)日：2006-10-05

申请号：DE102005014645

申请日：2005-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD

IPC: H01L27/24

Abstract: The electrode (4) has an electrically conducting electrode material (E) with a connection surface for a phase-transition-material. A number of isolation regions (I) are designed at the connection surface within the electrode material for reducing total contact area. The electrode material is coherently designed between the isolation regions, which extend from the connection surface to an opposite main surface. An independent claim is also included for a method of manufacturing a phase-transition-memory unit.

公开(公告)号：DE102005012112A1

公开(公告)日：2006-08-31

申请号：DE102005012112

申请日：2005-03-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ,  WILLER JOSEF

IPC: H01L27/115 ,  G11C16/00 ,  H01L21/8247

Abstract: A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.