公开(公告)号：WO03028104A3

公开(公告)日：2003-08-14

申请号：PCT/DE0202980

申请日：2002-08-14

Applicant: INFINEON TECHNOLOGIES AG ,  LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

Inventor： LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10891

Abstract: A trench capacitor (30) is arranged in a first trench (25) for production of a semiconductor memory (5). A first longitudinal trench (55) is arranged in the substrate (15) next to the first trench (25) and parallel thereto on the other side of the first trench (25), a second longitudinal trench (60) is arranged therein. A first spacer word line (70) is arranged in the first longitudinal trench (55) and a second spacer word line (75) is arranged in the second longitudinal trench (60). Connecting webs (80) are arranged in the first trench (25) between the first spacer word line (70) and the second spacer word line (75) with a thickness (110), which is smaller in the direction of the first spacer word line (70) than half the width of the first trench (25) in the direction of the first spacer word line (70).

Abstract translation: 为了制造半导体存储器（5），沟槽电容器（30）被布置在第一沟槽（25）中。 除了所述第一沟槽（25），第一纵向沟槽（55）和上第一沟槽并行（25），在所述基板的第二纵向沟槽（60）的另一侧（15）被布置。 在第一纵向沟槽（55）中设置第一间隔字线（70），在第二纵向沟槽（60）中设置第二间隔字线（75）。 在所述第一沟槽（25）的连接板（80）设置在所述第一间隔物的字线（70）和具有厚度（110）所述第二间隔的字线（75）（在第一间隔的字线70的方向之间 ）小于第一沟槽（25）朝向第一间隔字线（70）的宽度的一半。

公开(公告)号：WO02080240A2

公开(公告)日：2002-10-10

申请号：PCT/EP0203344

申请日：2002-03-25

Applicant: INFINEON TECHNOLOGIES AG ,  GOEBEL BERND ,  MOLL PETER ,  GUTSCHE MARTIN ,  SEIDL HARALD

Inventor： GOEBEL BERND ,  MOLL PETER ,  GUTSCHE MARTIN ,  SEIDL HARALD

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/8242

CPC classification number: H01L27/10867 ,  H01L21/0337 ,  H01L21/31116

Abstract: The invention relates to a lithographic method for removing a thin masking layer, particularly a Si3N4 layer on a side of a recess in a semi-conductor arrangement. According to the invention, an ion beam is orientated in an inclined manner at a certain angle towards the recess, enabling the thin masking layer to be removed in the regions exposed to the beams.

Abstract translation: 公开了一种光刻工艺的薄掩模层的去除，特别是氮化硅衬垫，在一侧上的凹槽中的半导体器件。 根据本发明，一个离子束以一定角度朝向斜到凹部中，从而将薄掩模层在照射区域移除被提供。

公开(公告)号：WO2005033358A3

公开(公告)日：2005-07-21

申请号：PCT/EP2004010892

申请日：2004-09-29

Applicant: INFINEON TECHNOLOGIES AG ,  GUTSCHE MARTIN ,  KREUPL FRANZ ,  PAMLER WERNER ,  SEIDEL ROBERT

Inventor： GUTSCHE MARTIN ,  KREUPL FRANZ ,  PAMLER WERNER ,  SEIDEL ROBERT

IPC: C23C16/02 ,  C23C16/04 ,  C23C16/26 ,  C23C16/44 ,  C23C16/455 ,  H01L21/3205

CPC classification number: C23C16/0209 ,  C23C16/045 ,  C23C16/26 ,  C23C16/45557

Abstract: The invention relates to a method for depositing a carbon material (17) in or on a substrate (14). Said method comprises the following steps: the inside (10') of a processing chamber (10) is heated to a pre-determined temperature; the substrate (14) is introduced into the processing chamber (10); the air in the processing chamber (10) is evacuated until a pre-determined pressure or a lower pressure is reached; a gas (12) containing at least carbon is introduced until a second pre-determined pressure is reached, that is higher than the first pre-determined pressure; and the carbon material (17) is deposited on a surface or in a recess (15), from the gas (12) containing carbon. The invention also relates to a semiconductor contact device.

Abstract translation: 本发明提供了用于在或基板（14）上沉积的碳材料（17），其包括以下步骤的方法：处理室（10）加热的内部空间（10“）到预定的温度; 放置在处理室中的基板（14）（10）; 抽空所述处理室（10）到第一预定压力或更低; 引入气体（12），其具有至少碳，​​直到达到第二预定压力，其比第一预定压力更高; 和沉积所述碳材料（17）上的表面上或在从含碳气体（12）的凹部（15）。 本发明还提供了一种半导体接触装置。

公开(公告)号：DE69935100D1

公开(公告)日：2007-03-29

申请号：DE69935100

申请日：1999-08-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ,  STROBL PETER ,  WEGE MP FE PI ,  LUEKEN EIKE ,  STOJAKOVIC GEORG ,  SPULER BRUNO

IPC: H01L21/302 ,  H01L21/3213 ,  C23C16/18 ,  H01L21/02 ,  H01L21/3065

Abstract: A method for reducing polymer deposition on vertical surfaces of metal lines etched from a metallization layer disposed above a substrate. The method includes forming a hard mask layer above the metallization layer and providing a photoresist mask above the hard mask layer. The method further includes employing the photoresist mask to form a hard mask from the hard mask layer. The hard mask has patterns therein configured to form the metal lines in a subsequent plasma-enhanced metallization etch. There is also included removing the photoresist mask. Additionally, there is included performing the plasma-enhanced metallization etch employing the hard mask and an etchant source gas that includes Cl2 and at least one passivation-forming chemical, wherein the plasma-enhanced metallization etch is performed without employing photoresist to reduce the polymer deposition during the plasma-enhanced metallization etch.

公开(公告)号：DE69834686D1

公开(公告)日：2006-07-06

申请号：DE69834686

申请日：1998-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TOBBEN DIRK ,  SPULER BRUNO ,  GUTSCHE MARTIN ,  WEIGAND PETER

IPC: H01L21/768 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L23/12 ,  H05K1/00 ,  H05K3/06 ,  H05K3/22 ,  H05K3/24

Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer is formed by a spinning-on an organic polymer, for example an organic polymer having silicon, or a flowable oxide, or a hydrogensilsequioxane, or divinyl-siloxane-benzocyclobutene. The metal layer is etched using reactive ion etching. The planarization layer is removed using a wet chemical etch.

公开(公告)号：DE102004007410B4

公开(公告)日：2006-01-19

申请号：DE102004007410

申请日：2004-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119

Abstract: The invention provides a method for fabricating a memory cell for storing electric charge, which has a substrate ( 101 ), which forms a first electrode, a trench-like recess ( 102 ) etched into the substrate ( 101 ), conductive material, which is provided as a projection in a central region of the trench-like recess ( 102 ) and spaced apart from the side walls ( 107 ) of the trench-like recess ( 102 ) and is in electrical contact with the substrate at the base ( 104 ) of the trench-like recess ( 102 ), a dielectric layer ( 108 ), which has been deposited on the side walls ( 107 ) of the trench-like recess ( 102 ), the base ( 104 ) of the trench-like recess ( 102 ) and the surfaces of the conductive material ( 105 ), and an electrode layer ( 110 ), which has been deposited on the dielectric layer ( 108 ) and forms a second electrode.

公开(公告)号：DE10345475A1

公开(公告)日：2005-05-04

申请号：DE10345475

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  HAPP THOMAS ,  PINNOW CAY-UWE ,  GUTSCHE MARTIN

IPC: G03G15/02 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

Abstract: A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

公开(公告)号：DE10248980A1

公开(公告)日：2004-05-06

申请号：DE10248980

申请日：2002-10-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN

IPC: C23C16/02 ,  C23C16/04 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242

Abstract: Production of structured silicon dioxide layers on process surfaces arranged perpendicular or slanted towards a substrate surface comprises preparing a substrate (4) with a relief in a process chamber, forming a starter layer (17) with leaving groups substituted by hydroxyl groups on sections of the process surfaces which extend from the substrate surface up to a determined covering depth of the relief, and applying tris(tert.-butoxy)silanol to the substrate so that a silicon dioxide layer (18) is selectively grown on the starter layer.

公开(公告)号：DE10208450A1

公开(公告)日：2003-09-11

申请号：DE10208450

申请日：2002-02-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAENGER ANNETTE ,  SELL BERNHARD ,  SEIDL HARALD ,  HECHT THOMAS ,  GUTSCHE MARTIN

IPC: C23C16/34 ,  C23C16/40 ,  C23C16/42 ,  C23C16/44 ,  C23C16/455 ,  C23C16/46 ,  C23C16/48 ,  C23C16/30

Abstract: Process chamber for producing a layer of material on sections of a surface (8) of a substrate (3) comprises: holding unit (2) for substrate; feeding and removal units (6) for gas phases of chemical precursors of the layer material; substrate feeding device (11) for introducing substrate into process chamber; heating source (9) for heating the substrate and/or substrate surface; and control unit. The control unit is used for sequentially introducing the chemical precursor compounds. The heating source (9) is formed as a radiation source, by means of which the temperature on the substrate surface can be changed in steps of more than 100 K per second. The radiation source is a heating lamp and is arranged in the chamber inner chamber (5) of the process chamber enclosed by a chamber wall (4). An Independent claim is also included for a process for depositing a layer of material on sections of a surface of a substrate.

公开(公告)号：DE10142580A1

公开(公告)日：2003-03-27

申请号：DE10142580

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ,  HECHT THOMAS ,  LEONHARDT MATTHIAS ,  SCHROEDER UWE

IPC: H01L21/8242