公开(公告)号：DE60107219D1

公开(公告)日：2004-12-23

申请号：DE60107219

申请日：2001-01-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： MUELLER GERHARD ,  HANSON DAVID R ,  BAILEY W

IPC: G11C5/06 ,  H03K19/0185 ,  H03K19/094 ,  G11C7/00 ,  H03K3/00

Abstract: A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention includes providing a semiconductor wafer having trenches formed in a trench region of a substrate, and forming a dielectric layer on the semiconductor wafer to fill the trenches whereby up features form on flat surfaces of the wafer. An edge portion of the semiconductor wafer is polished to remove a portion of the dielectric layer about the edge portions of the semiconductor wafer. The dielectric layer is polished across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the trench regions and the up features in a single polish step such that a mask step and etch step for reducing the up features are eliminated from the polishing process.

公开(公告)号：GB2352855B

公开(公告)日：2004-04-14

申请号：GB0009818

申请日：2000-04-25

Applicant: IBM ,  SIEMENS AG

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/401 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  G06F11/20

Abstract: A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.

公开(公告)号：DE60006720D1

公开(公告)日：2003-12-24

申请号：DE60006720

申请日：2000-12-04

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/10 ,  G11C7/00

Abstract: A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted. During an input prefetch, an interrupt may occur causing any received portion of the burst or prefetch to be stored in the array without disturbing memory locations corresponding to the balance or remaining bits of the prefetch.

公开(公告)号：DE69833415T2

公开(公告)日：2006-09-21

申请号：DE69833415

申请日：1998-09-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C7/06 ,  G11C11/403 ,  G11C5/02 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory having a plurality of memory cells arranged in rows and columns includes a bank of sense amplifiers disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier in the bank disposed in a sense amplifier region between a pair of complementary bit lines of an associated column. A master data line (MDQ) switch is located in a sense amplifier region occupying a corresponding row-wise space to at least one driver to provide space efficient placement thereof.

公开(公告)号：DE69831294T2

公开(公告)日：2006-06-08

申请号：DE69831294

申请日：1998-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C7/06 ,  G11C11/401 ,  G11C5/02 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

Abstract: The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.

公开(公告)号：DE60107219T2

公开(公告)日：2005-12-01

申请号：DE60107219

申请日：2001-01-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： MUELLER GERHARD ,  HANSON DAVID R ,  BAILEY W

IPC: G11C5/06 ,  H03K19/0185 ,  H03K19/094 ,  G11C7/00 ,  H03K3/00

Abstract: A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention includes providing a semiconductor wafer having trenches formed in a trench region of a substrate, and forming a dielectric layer on the semiconductor wafer to fill the trenches whereby up features form on flat surfaces of the wafer. An edge portion of the semiconductor wafer is polished to remove a portion of the dielectric layer about the edge portions of the semiconductor wafer. The dielectric layer is polished across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the trench regions and the up features in a single polish step such that a mask step and etch step for reducing the up features are eliminated from the polishing process.

公开(公告)号：DE69831294D1

公开(公告)日：2005-09-29

申请号：DE69831294

申请日：1998-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C11/401 ,  G11C5/02 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/06

Abstract: The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.

公开(公告)号：DE60105261D1

公开(公告)日：2004-10-07

申请号：DE60105261

申请日：2001-01-26

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  HANSON R

IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  G11C5/06 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094 ,  G11C7/00

Abstract: A bidirectional full swing voltage repeater implemented on a signal line of an integrated circuit, which includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional repeater circuit coupled between a first portion of the signal line and a second portion of the signal line. The first full-swing unidirectional repeater is configured to pass a first full swing signal from the first portion of the signal line to the second portion of the signal line when the first enable signal is enabled. The second full-swing unidirectional repeater circuit is coupled between the first portion of the signal line and the second portion of the signal line. The second full-swing unidirectional repeater circuit is configured to pass a second full swing signal from the second portion of the signal line to the first portion of the signal line when the second enable signal is enabled, wherein the first full-swing unidirectional repeater circuit and the second full-swing unidirectional repeater circuit are tri-stated when both the first enable signal and the second enable signal are disabled.

公开(公告)号：DE60104979D1

公开(公告)日：2004-09-23

申请号：DE60104979

申请日：2001-01-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON R ,  MUELLER GERHARD

IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  G11C5/06 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094 ,  G11C7/00

Abstract: A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below VDD. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to receive the first reduced voltage signal on the signal line. The input stage is also coupled to a level shifter stage that is arranged to output a set of level shifter stage control signals responsive to the first reduced voltage signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the first reduced voltage signal. There is further included coupling the output node to the second portion of the signal line. The output node also is coupled to an output stage of the reduced voltage repeater circuit. The output stage is configured to output the second reduced voltage signal on the output node responsive to the set of level shifter stage control signals. A voltage range of the second reduced voltage signal is lower than the voltage range of the set of level shifter stage control signals.

公开(公告)号：DE69822280D1

公开(公告)日：2004-04-15

申请号：DE69822280

申请日：1998-12-18

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

Abstract: Disclosed is a semiconductor memory employing a hierarchical bitline architecture which allows for a widened master bitline pitch as well as low bitline capacitance. In an exemplary embodiment, the memory (30) includes a plurality of memory cells (MC) arranged in rows and columns for storing data. Each column has at least one sense amplifier (SAi), at least one pair of master bitlines (MBLi, MBLi) operatively coupled to the sense amplifier, and at least two pairs of local bitlines (LBL1i, LBL1i, LBL2i, LBL2i), coupled to memory cells and selectively coupled to the sense amplifier. At least one of the local bitline pairs is selectively coupled to the sense amplifier via the master bitline pair. Each master bitline pair has a length shorter than a column length, and the master bitlines are arranged in an interleaved configuration. The pitch of at least a portion of at least some of the master bitlines is greater than the local bitline pitch. The master bitlines may be arranged in either folded or open configurations. The master bitline pitch may be about twice the local bitline pitch.