公开(公告)号：DE69834540D1

公开(公告)日：2006-06-22

申请号：DE69834540

申请日：1998-12-18

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C7/00 ,  G11C11/401 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14 ,  G11C11/408 ,  G11C11/409 ,  G11C16/06

Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F , includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

公开(公告)号：DE69833415D1

公开(公告)日：2006-04-20

申请号：DE69833415

申请日：1998-09-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C7/06 ,  G11C11/403 ,  G11C5/02 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory having a plurality of memory cells arranged in rows and columns includes a bank of sense amplifiers disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier in the bank disposed in a sense amplifier region between a pair of complementary bit lines of an associated column. A master data line (MDQ) switch is located in a sense amplifier region occupying a corresponding row-wise space to at least one driver to provide space efficient placement thereof.

公开(公告)号：DE60110297T2

公开(公告)日：2006-02-09

申请号：DE60110297

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/413 ,  G06F11/20 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

Abstract: A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially. The actual time multiplexing operation for performing the transfer is preferably enabled only after the chip power-up state.

公开(公告)号：DE60011190T2

公开(公告)日：2005-06-30

申请号：DE60011190

申请日：2000-07-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  KIRIHATA TOSHIAKI ,  DANIEL GABRIEL ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

公开(公告)号：DE69833093D1

公开(公告)日：2006-03-30

申请号：DE69833093

申请日：1998-09-04

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  WONG HING ,  KRSNKI BOZIDAR

IPC: G01R31/28 ,  G11C29/00 ,  G11C11/401 ,  G11C29/04 ,  G11C29/50 ,  G11C29/56

Abstract: The method involves generating a dummy timing cycle for disabling bitline equalizer by supplying a negative test pulse. The bitline equaliser is disabled to set up a floating bitline test mode. A row address strobe signal is enabled and read operation is started in a normal mode. Defective bitlines are detected during dummy timing cycles.

公开(公告)号：DE10315050A1

公开(公告)日：2003-11-27

申请号：DE10315050

申请日：2003-04-02

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD ,  HANSON DAVID

IPC: H03K19/0185 ,  H03L5/00

Abstract: A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

公开(公告)号：DE10314615A1

公开(公告)日：2003-10-23

申请号：DE10314615

申请日：2003-04-01

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: H03F3/04 ,  H03K19/0175 ,  H03K19/094

Abstract: A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.

公开(公告)号：DE69822280T2

公开(公告)日：2005-02-24

申请号：DE69822280

申请日：1998-12-18

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

Abstract: Disclosed is a semiconductor memory employing a hierarchical bitline architecture which allows for a widened master bitline pitch as well as low bitline capacitance. In an exemplary embodiment, the memory (30) includes a plurality of memory cells (MC) arranged in rows and columns for storing data. Each column has at least one sense amplifier (SAi), at least one pair of master bitlines (MBLi, MBLi) operatively coupled to the sense amplifier, and at least two pairs of local bitlines (LBL1i, LBL1i, LBL2i, LBL2i), coupled to memory cells and selectively coupled to the sense amplifier. At least one of the local bitline pairs is selectively coupled to the sense amplifier via the master bitline pair. Each master bitline pair has a length shorter than a column length, and the master bitlines are arranged in an interleaved configuration. The pitch of at least a portion of at least some of the master bitlines is greater than the local bitline pitch. The master bitlines may be arranged in either folded or open configurations. The master bitline pitch may be about twice the local bitline pitch.

公开(公告)号：DE69911364T8

公开(公告)日：2004-11-25

申请号：DE69911364

申请日：1999-12-20

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G06F11/20

Abstract: The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.

公开(公告)号：DE60006720T2

公开(公告)日：2004-09-23

申请号：DE60006720

申请日：2000-12-04

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/10 ,  G11C7/00

Abstract: A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted. During an input prefetch, an interrupt may occur causing any received portion of the burst or prefetch to be stored in the array without disturbing memory locations corresponding to the balance or remaining bits of the prefetch.