公开(公告)号：US20230197593A1

公开(公告)日：2023-06-22

申请号：US17553214

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Sivaseetharaman PANDI ,  Andrew P. COLLINS ,  Arghya SAIN ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a core, where the core comprises glass, and a first via through the core. In an embodiment, a first fin extends out laterally from the first via. In an embodiment, the electronic package further comprises a second via through the core, and a second fin extending out laterally from the second via. In an embodiment, a face of the first fin overlaps a face of the second fin.

公开(公告)号：US20230099632A1

公开(公告)日：2023-03-30

申请号：US17485248

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Aleksandar ALEKSOV ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01L23/15 ,  H01L27/02

Abstract: Embodiments disclosed herein include disaggregated die modules. In an embodiment, a disaggregated die module comprises a plurality of core logic blocks. In an embodiment, the disaggregated die module further comprises a first IO interface, where the first IO interface is adjacent to an edge of the disaggregated die module, and a second IO interface, where the second IO interface is set away from the edge of the disaggregated die module.

公开(公告)号：US20220416391A1

公开(公告)日：2022-12-29

申请号：US17356023

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Neelam PRABHU GAUNKAR ,  Veronica STRONG ,  Aleksandar ALEKSOV

IPC: H01P3/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01P11/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to positioning signal and ground vias, or ground planes, in a glass core to control impedance within a package. Laser-assisted etching processes may be used to create vertical controlled impedance lines to enhance bandwidth and bandwidth density of high-speed signals on a package. Other embodiments may be described and/or claimed.

公开(公告)号：US20220415779A1

公开(公告)日：2022-12-29

申请号：US17357896

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01L23/15 ,  H01L21/48

Abstract: Embodiments disclosed herein include package substrates with angled vias and/or via planes. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a first pad is on the first surface, and a second pad on the second surface, where the second pad is outside a footprint of the first pad. In an embodiment, the package substrate further comprises a via through a thickness of the core, where the via connects the first pad to the second pad.

公开(公告)号：US20220406737A1

公开(公告)日：2022-12-22

申请号：US17349777

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING

IPC: H01L23/66 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a transceiver architecture for inter-die communication on-package using mm-wave/THz interconnects. In particular, amplifier-less transceivers are used in combination with on-package low loss transmission lines to provide inter-die communication. In embodiments, signals on the interconnect may be transmitted between up conversion mixers and down conversion mixers without any additional amplification. Other embodiments may be described and/or claimed.

公开(公告)号：US20220406725A1

公开(公告)日：2022-12-22

申请号：US17350175

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR ,  Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV ,  Johanna M. SWAN

IPC: H01L23/552 ,  H01L23/15 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to glass interposers or substrates that may be created using a glass etching process to enable highly integrated modules. Planar structures, which may be vertical planar structures, created within the glass interposer may be used to provide shielding for conductive vias in the glass interposer, to increase the signal density within the glass substrate and to reduce cross talk. Other embodiments may be described and/or claimed.

公开(公告)号：US20220406686A1

公开(公告)日：2022-12-22

申请号：US17349695

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Neelam PRABHU GAUNKAR ,  Georgios C. DOGIAMIS ,  Veronica STRONG

IPC: H01L23/473 ,  H01L23/13 ,  H01L23/15 ,  H01L23/467 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a buildup layer is over the first surface of the core. In an embodiment, a channel is through the core, where the channel extends in a direction that is substantially parallel to the first surface.

公开(公告)号：US20220406616A1

公开(公告)日：2022-12-22

申请号：US17349667

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Veronica STRONG ,  Aleksandar ALEKSOV ,  Georgios C. DOGIAMIS ,  Telesphor KAMGAING ,  Neelam PRABHU GAUNKAR

IPC: H01L21/48 ,  H01L23/498

Abstract: Embodiments disclosed herein include package substrates and methods of fabricating such substrates. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. The package substrate further comprises a via hole through the core. In an embodiment the via hole comprises a first portion, a second portion, and a perforated ledge between the first portion and the second portion. In an embodiment, the package substrate further comprises a via filling the via hole.

公开(公告)号：US20220404568A1

公开(公告)日：2022-12-22

申请号：US17350809

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR ,  Georgios C. DOGIAMIS

IPC: G02B6/42

Abstract: Embodiments disclosed herein include electronic packages with a core that includes an optical waveguide and methods of forming such electronic packages. In an embodiment, a package substrate comprises a core, and a photonics die embedded in the core. In an embodiment, the electronic package further comprises an optical waveguide embedded in the core. In an embodiment, the optical waveguide optically couples the photonics die to an edge of the core.

公开(公告)号：US20220084965A1

公开(公告)日：2022-03-17

申请号：US17528049

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Sri Ranga Sai BOYAPATI ,  Kristof DARMAWIKARTA ,  Eyal FAYNEH ,  Ofir DEGANI ,  David LEVY ,  Johanna M. SWAN

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.