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公开(公告)号：US20180329478A1
公开(公告)日：2018-11-15
申请号：US16043738
申请日：2018-07-24
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
IPC: G06F1/32 , H04W88/02 , H04W52/02 , G06F12/084 , G06F9/4401 , G06F9/50 , G06F13/24
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：US20170330040A1
公开(公告)日：2017-11-16
申请号：US15662815
申请日：2017-07-28
Applicant: Intel Corporation
Inventor： Shayok Chakraborty , Omesh Tickoo , Ravishankar Iyer
Abstract: System, apparatus, method, and computer readable media for on-the-fly captured video summarization. A video stream is incrementally summarized in concurrence with generation of the stream by a camera module. Saliency of the video stream summary is maintained as the stream evolves by updating the summary to include only the most significant frames. In one exemplary embodiment, saliency is determined by optimizing an objective function including terms that are indicative of both the diversity of a selection, and how representative the selection is to the processed portion of the video data corpus. A device platform including a CM and comporting with the exemplary architecture may provide video camera functionality at ultra-low power, and/or with ultra-low storage resources, and/or with ultra-low communication channel bandwidth.
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公开(公告)号：US09653070B2
公开(公告)日：2017-05-16
申请号：US13732329
申请日：2012-12-31
Applicant: Intel Corporation
Inventor： Jenny Chang , Michael E. Deisher , Ravishankar Iyer
CPC classification number: G10L15/14
Abstract: A disclosed speech processor includes a front end to receive a speech input and generate a feature vector indicative of a portion of the speech input and a Gaussian mixture (GMM) circuit to receive the feature vector, model any one of a plurality of GMM speech recognition algorithms, and generate a GMM score for the feature vector based on the GMM speech recognition algorithm modeled. In at least one embodiment, the GMM circuit includes a common compute block to generate feature a vector sum indicative of a weighted sum of differences squares between the feature vector and a mixture component of the GMM speech recognition algorithm. In at least one embodiment, the GMM speech recognition algorithm being modeled includes a plurality of Gaussian mixture components and the common compute block is operable to generate feature vector scores corresponding to each of the plurality of mixture components.
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54.发明授权公开(公告)号：US09563579B2
公开(公告)日：2017-02-07
申请号：US13780117
申请日：2013-02-28
Applicant: Intel Corporation
Inventor： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Ravishankar Iyer , Quang T. Le , Ravi Kolagotla , Ioannis T. Schoinas , Jose S. Niell
CPC classification number: G06F13/00 , G06F9/00 , G06F13/1626 , Y02D10/14
Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有相关联的顺序标识符和在存储器请求完成之前指示最大等待时间的最后期限值。 响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。 描述和要求保护其他实施例。
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公开(公告)号：US20160171739A1
公开(公告)日：2016-06-16
申请号：US14567117
申请日：2014-12-11
Applicant: Intel Corporation
Inventor： Glen J. Anderson , Wendy March , Kathy Yuen , Ravishankar Iyer , Omesh Tickoo , Jeffrey M. Ota , Michael E. Kounavis
CPC classification number: G06T13/80 , G06T11/60 , G06T19/006 , G11B27/036 , G11B27/28 , H04S7/303 , H04S2400/11 , H04S2400/15
Abstract: Apparatuses, methods and storage media for providing augmented reality (AR) effects in stop-motion content are described. In one instance, an apparatus may include a processor, a content module to be operated by the processor to obtain a plurality of frames having stop-motion content, some of which may include an indication of an augmented reality effect, and an augmentation module to be operated by the processor to detect the indication of the augmented reality effect and add the augmented reality effect corresponding to the indication to some of the plurality of frames. Other embodiments may be described and claimed.
Abstract translation: 描述了用于在停止运动内容中提供增强现实（AR）效应的装置，方法和存储介质。 在一种情况下，装置可以包括处理器，要由处理器操作的内容模块以获得具有停止运动内容的多个帧，其中一些帧可以包括增强现实效果的指示，以及增强模块， 由处理器操作以检测增强现实效果的指示，并将对应于指示的增强现实效果添加到多个帧中的一些帧。 可以描述和要求保护其他实施例。
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Patent Agency Ranking
56.发明申请公开(公告)号：US20160132354A1
公开(公告)日：2016-05-12
申请号：US14995198
申请日：2016-01-13
Applicant: Intel Corporation
Inventor： Ravishankar Iyer , Sadagopan Srinivasan , LI ZHAO , Rameshkumar G. Illikkal
CPC classification number: G06F9/4881 , G06F9/5027 , G06F11/3409 , G06F11/3433 , G06F12/084 , G06F2201/88 , G06N5/02 , Y02D10/13 , Y02D10/22 , Y02D10/34
Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.
Abstract translation: 描述了在异构多处理器计算平台中调度应用程序的方法和装置。 在一个实施例中，处理器的多个处理器核的性能（例如，执行性能和/或功耗性能）的信息被存储（并被跟踪）在计数器和/或表中。 处理器中的逻辑根据存储的信息确定哪个处理器内核应该执行应用程序。 还要求和公开其它实施例。
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公开(公告)号：US09329900B2
公开(公告)日：2016-05-03
申请号：US13730539
申请日：2012-12-28
Applicant: Intel Corporation
Inventor： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
CPC classification number: G06F9/5044 , G06F9/45533 , G06F9/5077 , G06F9/5094 , G06F15/80 , Y02D10/22
Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.
Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同 虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心集合内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行 从第一组或第二组物理处理器到第一虚拟处理器。
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公开(公告)号：US20160077844A1
公开(公告)日：2016-03-17
申请号：US14947321
申请日：2015-11-20
Applicant: INTEL CORPORATION
Inventor： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
CPC classification number: G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
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公开(公告)号：US08861847B2
公开(公告)日：2014-10-14
申请号：US13724150
申请日：2012-12-21
Applicant: Intel Corporation
CPC classification number: G06K9/4652 , G06K9/00375
Abstract: A system and method for detecting human skin tone in one or more images. The system includes an image processing module configured to receive an image and provide contrast enhancement of the image so as to compensate for background illumination in the image. The image processing module is further configured to detect and identify regions of the contrast-enhanced image containing human skin tone based, at least in part, on the utilization of multiple color spaces and adaptively generated thresholds for each color space. A system and method consistent with the present disclosure is configure to provide accurate detection of human skin tone while accounting for variations in skin appearance due to a variety of factors, including background illumination and objects.
Abstract translation: 一种用于在一个或多个图像中检测人肤色调的系统和方法。 该系统包括被配置为接收图像并且提供图像的对比度增强以便补偿图像中的背景照明的图像处理模块。 图像处理模块还被配置为至少部分地基于多个颜色空间的利用和针对每个颜色空间的自适应生成的阈值来检测和识别包含人肤色的对比度增强图像的区域。 与本公开一致的系统和方法被配置为提供对人肤色调的准确检测，同时考虑到由于各种因素（包括背景照明和物体）引起的皮肤外观的变化。
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公开(公告)号：US12198186B2
公开(公告)日：2025-01-14
申请号：US17401575
申请日：2021-08-13
Applicant: Intel Corporation
Inventor： Andrew Herdrich , Edwin Verplanke , Ravishankar Iyer , Christopher Gianos , Jeffrey D. Chamberlain , Ronak Singhal , Julius Mandelblat , Bret Toll
IPC: G06Q40/03 , G06F12/0875 , G06F12/0897
Abstract: Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.
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