公开(公告)号：WO2010016879A8

公开(公告)日：2010-09-16

申请号：PCT/US2009004443

申请日：2009-08-03

Applicant: MICRON TECHNOLOGY INC ,  MANNING TROY A

Inventor： MANNING TROY A

IPC: G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C8/10 ,  G11C11/4087

Abstract: Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 电子设备，系统和方法可以操作结构以访问存储器阵列的一部分行而不访问整个行。 公开了另外的设备，系统和方法。

公开(公告)号：WO9839846A3

公开(公告)日：1998-12-03

申请号：PCT/US9804346

申请日：1998-03-05

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C7/00 ,  G11C7/22 ,  H03K5/13 ,  H03L7/081

CPC classification number: G11C7/222 ,  G11C7/22 ,  H03K5/131 ,  H03L7/0814

Abstract: A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.

Abstract translation: 延迟锁定环路将二进制耦合电容器并入电容器组，以沿延迟线产生可变电容。 可变电容允许可变延迟线的延迟变化。 响应于输入时钟信号，可变延迟线产生延迟输出时钟信号，其在竞争检测电路处与输入时钟信号进行比较。 如果延迟的时钟信号超前输入时钟信号，则竞争检测电路递增控制二进制耦合电容器的计数器。 递增计数器通过将附加电容耦合到可变延迟线来延迟电容，以延迟延迟时钟信号的传播。 如果延迟时钟信号滞后于原始时钟信号，则竞争检测电路递减计数器以减小电容，由此减小可变延迟线的延迟。 竞争检测电路包括仲裁电路，该仲裁电路检测延迟时钟信号和可变时钟信号何时基本同步并且响应于禁止计数器递增或递减。

公开(公告)号：WO2015187606A3

公开(公告)日：2017-05-04

申请号：PCT/US2015033651

申请日：2015-06-02

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A ,  MURPHY RICHARD C

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/06 ,  G06F11/10 ,  G06F11/1048 ,  G11C7/10 ,  G11C7/22 ,  G11C7/24 ,  G11C11/4078 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.

Abstract translation: 本公开包括涉及使用感测电路的奇偶校验确定的设备和方法。 示例性方法可以包括使用感测电路来通过确定与数据值的数量对应的奇偶校验值来保护存储在耦合到阵列的感测线的相应数量的存储器单元中的多个数据值，而无需从阵列传输数据 通过输入/输出线。 例如，奇偶校验值可以由多个XOR操作确定。 该方法可以包括将奇偶校验值存储在耦合到感测线的另一存储器单元中。

公开(公告)号：WO2006121874A3

公开(公告)日：2007-08-02

申请号：PCT/US2006017439

申请日：2006-05-04

Applicant: MICRON TECHNOLOGY INC ,  JOHNSON JAMES B ,  MANNING TROY A

Inventor： JOHNSON JAMES B ,  MANNING TROY A

IPC: G01R31/26

CPC classification number: G11C7/1039 ,  G11C7/1048 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/105 ,  G11C2207/2254

Abstract: A synchronous dynamic random access memory ("SDRAM") device (100) includes a pipelined write data path coupling data from a data bus to a DRAM array (122), and a pipelined read data path coupling read data from the array ((122) to the data bus. The SDRAM device also includes a bypass path allowing the write data in the write data path to be coupled directly to the read data path without firs being stored in the DRAM array. The write data are preferably coupled through the write data path by issuing a write command to the DRAM device, and the read data are preferably coupled through the read data path by issuing a read command to the DRAM device. The memory array is inhibited from responding to these commands so that the write data are not stored in the array, and read data from the array are not coupled to the read data path.

Abstract translation: 同步动态随机存取存储器（“SDRAM”）装置（100）包括将从数据总线到DRAM阵列（122）的数据耦合的流水线写入数据路径，以及将读取数据从阵列（（122 ）SDRAM装置还包括旁路路径，允许写入数据路径中的写入数据直接耦合到读取数据路径，而没有保存在DRAM阵列中的数据，写入数据优选地通过写入 通过向DRAM设备发出写入命令，读取数据优选地通过读取数据路径耦合到DRAM设备，读取命令被禁止响应于这些命令，使得写入数据是 不存储在阵列中，并且从阵列读取数据不会耦合到读取的数据路径。

公开(公告)号：WO02099661A2

公开(公告)日：2002-12-12

申请号：PCT/US0217849

申请日：2002-06-06

Applicant: MICRON TECHNOLOGY INC

Inventor： JOHNSON BRIAN ,  KEETH BRENT ,  MANNING TROY A

IPC: G11C11/407 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C11/409 ,  G06F13/00

CPC classification number: G11C29/028 ,  G06F13/1694 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/401 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device is disclosed. The actual time of arrival of data at the inputs to a memory device is determined by sending back-to-back write commands along with the predetermined data pattern to the memory device. The data pattern is stored in a register and any difference between the predicted arrival time of the data and the actual arrival time of the data is determined by logic circuitry. Any determined difference can then be compensated for by delaying the start of the capture of the data at the memory device, thereby accurately aligning the start of the data capture and the arrival of the data at the memory device.

Abstract translation: 公开了一种用于准确地确定数据在存储器件相对于写入时钟的实际到达以精确对准数据捕获的开始和数据到达存储器件的方法和装置。 将数据到输入到存储器件的实际时间通过与存储器件一起发送背靠背写入命令以及预定数据模式来确定。 数据模式存储在寄存器中，数据的预计到达时间与数据的实际到达时间之间的任何差异由逻辑电路确定。 然后可以通过延迟在存储器件处捕获数据的开始来补偿任何确定的差异，从而将数据捕获的开始和数据的到达准确地对准在存储器件处。

公开(公告)号：WO9944752A3

公开(公告)日：1999-10-21

申请号：PCT/US9904903

申请日：1999-03-05

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G06F11/22 ,  G06F11/00 ,  G11C11/401 ,  G11C29/44 ,  G11C29/50 ,  H01L21/82 ,  G11C29/00

CPC classification number: G06F11/006 ,  G11C29/44 ,  G11C29/50

Abstract: A method and circuit for recording the performance parameters in an integrated circuit. A speed grade register is programmed by the manufacturer with an indication of the speed capability of the integrated circuit. The integrated circuit also includes a clock speed register that is programmed by the user with an indication of the frequency of a clock signal that will be used to synchronize the operation of the integrated circuit. The speed grade and clock speed indications are used to select a set of performance data from a performance data register to provide an indication of the performance of the integrated circuit at the indicated speed grade and clock speed.

Abstract translation: 用于在集成电路中记录性能参数的方法和电路。 速度等级寄存器由制造商编程，指示集成电路的速度能力。 该集成电路还包括时钟速度寄存器，该时钟速度寄存器由用户通过指示将被用于同步集成电路的操作的时钟信号的频率来进行编程。 速度等级和时钟速度指示用于从性能数据寄存器中选择一组性能数据，以指示速度等级和时钟速度下集成电路的性能指标。

公开(公告)号：WO2015187901A1

公开(公告)日：2015-12-10

申请号：PCT/US2015034101

申请日：2015-06-04

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A ,  MURPHY RICHARD C

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4093

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a compute component. The sensing circuitry is configured to invert a data value in the compute component.

Abstract translation: 本公开包括与使用感测电路执行逻辑运算相关的装置和方法。 示例性设备包括耦合到阵列的存储器单元阵列和感测电路。 感测电路包括计算组件。 感测电路被配置为反转计算组件中的数据值。

公开(公告)号：WO2007005218B1

公开(公告)日：2007-04-26

申请号：PCT/US2006023219

申请日：2006-06-14

Applicant: MICRON TECHNOLOGY INC ,  MARTIN CHRIS G ,  MANNING TROY A ,  KEETH BRENT

Inventor： MARTIN CHRIS G ,  MANNING TROY A ,  KEETH BRENT

IPC: G11C29/00

CPC classification number: G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

Abstract translation: 一种用于修复半导体存储器件的装置和方法包括第一存储器单元阵列，第一冗余单元阵列和修复电路，该修复电路被配置为非易失性地将指定至少一个故障存储器单元的第一地址存储在第一存储器单元阵列中。 第一易失性高速缓存存储对应于指定至少一个有缺陷的存储单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个故障存储单元的第一地址分配给第一易失性缓存。 当第一存储器访问对应于第一高速缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储器单元替换为第一存储器单元阵列中的至少一个有缺陷存储器单元。

公开(公告)号：WO2004001846A3

公开(公告)日：2004-10-28

申请号：PCT/US0321029

申请日：2003-06-18

Applicant: MICRON TECHNOLOGY INC ,  BATRA SHUBNEESH ,  CHAINE MICHAEL D ,  KEETH BRENT ,  AKRAM SALMAN ,  MANNING TROY A ,  JOHNSON BRIAN ,  MARTIN CHRIS G ,  MERRITT TODD A ,  SMITH ERIC J

Inventor： BATRA SHUBNEESH ,  CHAINE MICHAEL D ,  KEETH BRENT ,  AKRAM SALMAN ,  MANNING TROY A ,  JOHNSON BRIAN ,  MARTIN CHRIS G ,  MERRITT TODD A ,  SMITH ERIC J

IPC: H01L23/485 ,  H01L23/522 ,  H01L23/64

CPC classification number: H01L24/05 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01061 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105

Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels (M1, M2, M3, etc) is described. The method comprises forming a bond pad (20) at least partially exposed at the top surface of the integrated circuit, forming a metal pad (22) on the metal level (42) below the bond pad (20) and forming an underlying metal pad (26b) on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads (22, 26b) to the area of the bond pad (20) is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

Abstract translation: 描述了一种降低具有三个或更多个金属水平（M1，M2，M3等）的集成电路中的寄生电容的方法。 该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘（20），在接合焊盘（20）下方的金属层（42）上形成金属焊盘（22），并形成下面的金属焊盘 （26b）在所述一个或多个下层金属层中的每一个上。 在所示实施例中，下面的金属焊盘（22,26b）中的至少一个的面积与焊盘（20）的面积之比小于30％。 寄生电容因此大大降低，信号传播速度提高。

公开(公告)号：WO02069341A3

公开(公告)日：2002-11-28

申请号：PCT/US0202764

申请日：2002-02-01

Applicant: MICRON TECHNOLOGY INC

Inventor： JANZEN JEFFERY W ,  MANNING TROY A ,  MARTIN CHRIS G ,  KEETH BRENT

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/409

CPC classification number: G11C7/1066 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/409 ,  G11C2207/107 ,  G11C2207/2254 ,  G11C2207/2281

Abstract: The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.

Abstract translation: 通过使用至少一个标志信号来均衡高速同步存储器子系统中的多个存储器装置的读取等待时间。 标记信号具有等同的信号传播特性读取时钟信号，从而自动补偿信号传播的影响。 在检测到标志信号之后，存储装置将开始以预定数量的时钟周期输出与先前接收的读取命令相关联的数据。 对于标志信号中的每一个，存储器控制器在系统初始化时确定在发出读取命令和发出标志信号以均衡系统读取等待时间之间所需的延迟。 然后在存储器系统的正常操作期间将延迟应用于读取事务。