公开(公告)号：JPH04214653A

公开(公告)日：1992-08-05

申请号：JP41029190

申请日：1990-12-12

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768

Abstract: PURPOSE:To simplify the manufacturing process for wiring structure using a blanket W-CVD method and for its formation method and to enhance a throughput by a method wherein a close contact layer formed as a substratum for blanket W can be used also as a barrier metal used to form, e.g. an Al interconnection. CONSTITUTION:An opening 4 is formed in an insulating film 2 on, e.g. a silicon substrate 1; a metal layer 5 which is composed of a Ti layer 8, a TiON layer 9 and a Ti layer 10 is formed from the bottom part 4 in the opening 4 to the surface of the insulating film 2; in addition, a tungsten metal layer 6 as blanket W is formed on the whole surface of the metal layer 5 so to fill said opening 4; after that, at least the tungsten metal layer 6 is patterned; and a wiring pattern 7 is formed.

公开(公告)号：JPH04171726A

公开(公告)日：1992-06-18

申请号：JP29816790

申请日：1990-11-02

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213

Abstract: PURPOSE:To speed up multilayered dry-etching and to improve anisotropy by making the etching gas contain at least O2 gas and Br-based gas or F-based gas in addition to them. CONSTITUTION:After transistors are formed on a silicon substrate 1 and coated with a lower layer wiring 22 for its patterning, it is entirely overlaid with an insulating layer 23 such as SiO2 or the like. Further, a base material layer 2 made of Al or the like, a lower resist layer 3 of polyimide or the like, an SGO intermediate layer 4, and an upper resist layer 5 are formed one after another. For example, CBr4 and O2 with a flow rate ratio of 30:70 and a pressure of 5-10mTorr are used as the etching gas, this multilayered resist layer is gradually etched away finally to obtain a wiring pattern 7 of the base layer 2. Even this way of etching with O* radicals under a high pressure allows anisotropy to be kept enough by mixture of Br-based gas, thereby suppressing deposit of the base material layer 2 onto the resist layer 3. This can speed up multilayered dry-etching and improve anisotropy.

公开(公告)号：JPH0445533A

公开(公告)日：1992-02-14

申请号：JP15423290

申请日：1990-06-13

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L21/76 ,  H01L21/31 ,  H01L21/316 ,  H01L21/762

Abstract: PURPOSE:To attain a more enhanced flattened surface by setting a ratio of deposition speed 'a' between a horizontal direction and a vertical direction to 2y/x when burying and flattening a ground having a recessed section of width x and depth y based on a bias ECR-CVD process. CONSTITUTION:A recessed section 10 of a substrate, which is a base 1, is buried and flattened. In this case, the pressure is specified to be 9X10 Torr or below and the recessed section is buried and flattened based on a bias ECR-CVD process, thereby controlling the ratio 'a' of growth speed to the side wall and growth speed on a horizontal level to 1:2y/x to attain buried flatness. This construction makes it possible to embody the embedding at the same aspect ratio constantly, eliminate the generation of hollows, and bury fine apertures ranging from 0.3 to 0.35mum (width) to a satisfactory extent. It is also possible to carry out the embedding, inhibiting the dependence on embedding film thickness pattern.

公开(公告)号：JPH0430421A

公开(公告)日：1992-02-03

申请号：JP13416490

申请日：1990-05-25

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285

Abstract: PURPOSE:To simultaneously satisfy both selective growth property and heat- resisting property by a method wherein a film, which becomes the seed for selective growth, is formed on the side wall of a contact hole, and after the film which develops into a heat-resisting film has been formed on the bottom part, metal is selectively grown and buried. CONSTITUTION:First, an insulating film of SiO and the like is formed on the surface of a silicon substrate 11, a contact hole 13 having the prescribed size is opened, and for example, a phosphorus-doped a-Si film 16 is formed on the whole surface for the purpose of lowering contact resistance. Then, a TiN film 17 is formed on the a-Si film 16. Subsequently, using a bias-application type ECR plasma treating device of the same high frequency or other plasma treating device, the RiN on the coarse section, namely, the TiN film 17a on the side wall is removed by plasma etching. Then, a W 18 is formed using a selective W-CVD method. At this time, as a W 18 is grown with the a-Si film 16 on the side wall 15 as the seed of growth, a contact hole 13 can be filled up. Subsequently, after the a-Si film 16 and the TiN film 17 on the upper part have been removed using an anisotropic method and the like, an upper part wiring is formed using a sputtering method and the like.

公开(公告)号：JPH047825A

公开(公告)日：1992-01-13

申请号：JP10967190

申请日：1990-04-25

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768

Abstract: PURPOSE:To make a stable contact hole for enhancing the reliability upon the quality of a semiconductor device by a method wherein a barrier metal layer is formed on the bottom part of the contact hole to be thick in the peripheral parts and thin in the central part and later the contact hole is filled up with a high melting point metal. CONSTITUTION:Within plasma CVD, a barrier metal layer 4a comprising TiN is buried in a connecting hole 3 on an layer insulating film 2 equalizing the deposition rate and the etching rate with each other at the shoulder parts B, C of the connecting hole 3 by adjusting the feeding rates of TiCl4 and NH3 gas. Next, the barrier metal layer 4a is etched back to be left on the bottom part of the connecting hole 3 so that the residual barrier metal layer 4a may be thick in the peripheral parts and thin in the central part and later tungsten (W) 6 is selectively deposited to be buried in the connecting hole 3. Through these procedures, the thermal resistance of the barrier metal layer 4a can be enhanced thereby enabling the stable contact hole 3 to be made while enhancing the reliability upon the quality of the semiconductor device.

公开(公告)号：JPH03241857A

公开(公告)日：1991-10-29

申请号：JP4051790

申请日：1990-02-20

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L21/3205 ,  H01L21/768

Abstract: PURPOSE:To eliminate the imperfect connection of a selective growth metal film with an upper wiring due to the variation of the metal film in thickness by a method wherein a dummy layer specified in thickness is formed on an insulating film, a connection hole is provided to the insulating film and the dummy layer, a metal film is selectively grown, and the dummy layer is removed. CONSTITUTION:A dummy layer 3, whose thickness is almost within a variation range of a metal film in thickness at the selective growth it, is formed on an insulating film 2, a connection hole 4 is provided to the dummy layer 3 and the insulating film 2, a metal film 5 is selectively grown inside the connection hole 4, and then the dummy layer 3 is removed. For instance, the interlaminar insulating film 2 0.8mum or so in thickness is formed on the surface of a semiconductor substrate where a lower wiring 1 has been formed, and the dummy layer 3 of LP-Si3N4 0.2-0.4mum in thickness is formed thereon. Then, the connection hole 4 is formed through an anisotropic etching method, and an tungsten film 5 is made to grow inside the connection hole 4 through a selective tungsten CVD method. Then, the dummy layer 3 is removed, and an upper wiring 7 of aluminum which contains Si is formed through the intermediary of a barrier metal layer 6.

公开(公告)号：JPH03139858A

公开(公告)日：1991-06-14

申请号：JP27792989

申请日：1989-10-25

Applicant: SONY CORP

Inventor： SATO JUNICHI ,  GOCHO TETSUO ,  MORITA YASUSHI

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/762

Abstract: PURPOSE:To remove an insulating film at the outside of a trench and to make it possible to perform flat embedding even if a slope part is formed at the lower part of the side surface of the insulating film at the outside of the trench by forming an etching stop layer on a surface of a substrate before the formation of a trench beforehand. CONSTITUTION:An etching stop layer 6 is formed beforehand. A trench 2 and an insulating film 3 are formed. An insulating film 3a at the outside of the trench is returned to a horizontal state and etched. Thereafter, anisotropic etching is performed. Therefore the slope part at the bottom of the insulating film 3a at the outside of the trench can be completely removed. Thus, a space required for forming a resist film masking an insulating film 3 in the trench can be secured. The insulating film 3a at the outside of the trench can be completely removed. The surface part of the insulating film 3 in the trench is etched by anisotropic etching after the etching for restoring the horizontal state. Since the insulating film 3 is thickly formed by the thickness of the etching stop layer 6 originally, the surface of the insulating film 3 can be made flush with the height of the surface of the substrate by the anisotropic etching.

公开(公告)号：JPH03108720A

公开(公告)日：1991-05-08

申请号：JP24730489

申请日：1989-09-22

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522

Abstract: PURPOSE:To decrease the resistance of a contact part between an upper wiring layer and a high-melting-point metal film filling the connecting hole of an interlayer insulating film by filling the connecting hole with the high-melting-point metal film, and widening the area of the exposed surface of the high-melting-point metal film in the connecting hole before the formation of the upper wiring layer. CONSTITUTION:A connecting hole 4 is formed in an interlayer insulating film 3 on a conducting region 2. Then, a high-melting-point metal film 5 is selectively grown in the connecting hole 4. The connecting hole 4 is filled with the high-melting-point metal film 5. Then, treatment for increasing the area of the exposed surface of the high-melting-point metal film is performed. Then, an upper wiring layer 6 which is connected to the conducting region 2 through said high-melting-point metal film 5 is formed on the interlayer insulating film 3. For example, the tungsten film 5 is selectively grown in the contact hole 4 by a silane reduction method. Then, the device is exposed to Cl2 gas for forming WClx having high vapor pressure for about one minute. Thus a part of the surface of the tungsten 5 becomes WClx. Then SF6 is supplied as etching gas, and etching is performed. Then irregularities are formed on the tungsten 5. Thereafter, the upper wiring film 6 is formed.

公开(公告)号：JPH03108320A

公开(公告)日：1991-05-08

申请号：JP24585889

申请日：1989-09-21

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L21/205 ,  H01L21/20 ,  H01L21/263

Abstract: PURPOSE:To prevent the deterioration of film quality by conveying a preliminarily heated substrate in an optical CVD chamber and performing film deposition. CONSTITUTION:A semiconductor wafer 2 conveyed from a load lock chamber 1 to a preliminarily heating chamber 4 through a gate valve 3 is preliminarily heated, on a heating stage, at a specified temperature by a heater 6. The wafer 2 is conveyed in an optical CVD chamber 8 via a gate valve 7, mounted on a susceptor 10, and irradiated, via an ultraviolet ray transmitting window 9, with, e.g. excimer laser beam for activating reaction species. Optical CVD is performed by vertically projecting ultraviolet rays on the wafer 2 surface via the window 9. The wafer 2 subjected to optical CVD is conveyed in an unload lock chamber 12 and accommodated in a cassette. Since the wafer is heated at, e.g. 300 deg.C at the time of optical CVD, deposition of superior film quality can be obtained.

公开(公告)号：JPH0344473A

公开(公告)日：1991-02-26

申请号：JP17965289

申请日：1989-07-12

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: C23C16/50 ,  C23C16/511 ,  H01L21/205 ,  H01L21/31

Abstract: PURPOSE:To miniaturize the ECR plasma CVD device and to save manpower in the film forming process by arranging plural permanent magnets in the plasma producing chamber into which a gas and a microwave are introduced. CONSTITUTION:A microwave is introduced into the plasma producing chamber 2 provided with the permanent magnets 10 on its periphery through a waveguide 8 to convert the gas introduced from an inlet pipe 9 to plasma. The plasma current 14 is drawn out and introduced into a reaction chamber 1 from a window 6, the gaseous reactant introduced from an inlet pipe 5 is excited by the active molecule in the plasma, and a reaction is caused on a wafer 3 placed on a susceptor 4 to deposit a thin film. In this ECR plasma CVD device, plural magnets 12 are arranged in the plasma producing chamber 2. The magnetic field necessary to cause resonance is generated by the permanent magnets 10 and 12. Consequently, the device is miniaturized, and the manpower is saved in the film forming process.