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公开(公告)号：JPH08330977A
公开(公告)日：1996-12-13
申请号：JP814996
申请日：1996-01-22
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAGAMI TAMOTSU , YAMAMURA SHINICHI
Abstract: PURPOSE: To reproduce data from a recording medium, where data is recorded at a different transfer rate, at this transfer rate for recording. CONSTITUTION: Data is reproduced from the data recording medium like a disk where data is recorded at a different transfer rate together with a signal indicating this transfer rate. A process circuit 41 which reproduces a digital signal from the disk to demodulate it, an ECC decoder 42 which performs error correction processing of the reproduced digital signal with respect to each sector, and a multiplexer 43 which separates the signal subjected to error correction by the ECC decoder into digital data and the other signal are provided. Information of the transfer rate of recorded data is obtained from digital data, and data is reproduced at the transfer rate for recording in accordance with this information of the transfer rate.
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公开(公告)号：JPS6359220A
公开(公告)日：1988-03-15
申请号：JP20316386
申请日：1986-08-29
Applicant: SONY CORP
Inventor： YAMAMURA SHINICHI , SAKO YOICHIRO
Abstract: PURPOSE:To improve error correction capability by applying a correction when a code is enabled for 2-error detection and correction and the presence of 2-data errors is detected in generated series by the code if the two error data are consecutive and not applying correction when the two error data are not consecutive. CONSTITUTION:In detecting two data errors, when the error are consecutive, the error correction is applied and when the errors are not consecutive, no error correction is applied. Depending on the probability of error generation, mots of two error data is corrected. Even in looking over an error that three error data are regarded as two separate data error since the probability of two data consecution is low, the increase in the error due to overlooked error is less.
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公开(公告)号：JPS62173821A
公开(公告)日：1987-07-30
申请号：JP1550086
申请日：1986-01-27
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAMURA SHINICHI
IPC: H03M13/00
Abstract: PURPOSE:To simplify the constitution by equalizing the number of words included in the first sequence of an error correction code and that in the second sequence to share an encoder or decoder between these two sequences. CONSTITUTION:In two linear codes, namely, (n1, k1) code and (n2, k2) code, k1 and n1 are equalized to k2 and n2 respectively for the purpose of equalizing the number of words in the first sequence of the error correction code and that in the second sequence. In case of 512-byte information, k1 and k2 are set to 23, and n1 and n2 are set to 27, and a lead Solomon code (27, 23) is used as the first and second correction codes. A 12-byte header and a 4-byte CRC, namely 16 bytes are added to 512 bytes of information because information points have a 529 (23X23)-byte capacity, and one bit of '0' is added, and 529 bytes are obtained as the whole. Error correction codes C1- and C2- are added to them to obtain 27X27 bytes.
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公开(公告)号：JPS62161222A
公开(公告)日：1987-07-17
申请号：JP314886
申请日：1986-01-10
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAMURA SHINICHI
Abstract: PURPOSE:To correct effectively a burst error by inverting once the order of the 1st series correction processing and the 2nd series correction processing and limiting number of times of the inverting processing to a prescribed number or below when the error correction is disabled. CONSTITUTION:An address generating circuit 2 generates an address data reading a data of column block and a data of a row block alternately from the column block or the row block for decoding start from a memory 1. A control circuit 6 generates a control signal inverting once the correction processing of the column block and the row block when the error correction is disabled in applying correction processing alternately to the column and row blocks and supplied the control signal to the address generation circuit 2. Thus, a discrimination signal representing whether or not the correction is enabled is fed from the C2 decoder 5 to the control circuit 6. The number of times of the inverting processing is limited to a prescribed number or below to prevent the decoding time from being longer. Thus, the decoding time by the burst error is reduced.
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公开(公告)号：JPS62161221A
公开(公告)日：1987-07-17
申请号：JP314786
申请日：1986-01-10
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAMURA SHINICHI
Abstract: PURPOSE:To quicken the error detection by providing a means applying correction processing to an error correction code until a data request signal comes and a means applying error detection to an error detection code after the data request signal comes or the correction processing is finished. CONSTITUTION:A data of a matrix block is stored in a memory 1 and when the decoding is started, an input/output control circuit 3 supplies the data from the memory 1 to an error correction circuit 4 and when a correction end signal Pe is generated or a data request signal Rx is supplied, the input/output control circuit 3 supplies the data from the memory 1 to a CRC operation circuit 5. After the correction end signal Pe is generated, when the correction operation is transited to the error detection or the correction operation is transited to the error detection after the data request signal Rx comes, and in the latter case, even when he correction operation is not finished with respect to the matrix block, the error detection is transited. Thus, the data transmission is applied quickly.
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Patent Agency Ranking
公开(公告)号：JPS6129461A
公开(公告)日：1986-02-10
申请号：JP15150084
申请日：1984-07-21
Applicant: Sony Corp
Inventor： KOBAYASHI SHOEI , WADA TAKUYA , YAMAMURA SHINICHI
IPC: G11B20/12 , G11B7/0033 , G11B7/013 , G11B20/18
CPC classification number: G11B20/1809 , G11B7/0033 , G11B7/013
Abstract: PURPOSE:To attain reproduction with high reliability by delaying sequentially each word in the track direction and vertical direction to the track and applying scramble processing to apply error correction at generation of a burst error. CONSTITUTION:A data signal of 16 words per one block of an information data source 11 generating information data to be recorded is converted into data of 20 words per word by a coder 12 generating four check words by an error correction code. The data of the coder 12 is subjected to scramble processing at a circuit 13, where the data is converted into data of 20 words per block and it is extracted from an output terminal 14. Cutting data at the terminal 14 is recorded respectively to each track of a strip region of an optical recording card by one block each.
Abstract translation: 目的：为了通过对磁道的轨道方向和垂直方向顺序地延迟每个字来应用扰频处理以在产生突发错误时应用纠错来获得高可靠性的再现。 构成：生成要记录的信息数据的信息数据源11的每个块的16个字的数据信号由编码器12转换成每个字20个字的数据，该编码器12通过纠错码产生四个检查字。 编码器12的数据在电路13进行加扰处理，其中数据被转换成每块20个字的数据，并且从输出端子14中提取出编码器12的数据。终端14上的切割数据被分别记录到每个轨道 的光记录卡的条带区域分别为一个块。
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公开(公告)号：JPS58122675A
公开(公告)日：1983-07-21
申请号：JP526382
申请日：1982-01-16
Applicant: SONY CORP
Inventor： IHASHI TAKAO , AIDA SEIICHI , YAMAMURA SHINICHI , OGAWA HIROSHI
Abstract: PURPOSE:To release hang-up state automatically, by detecting the hang-up state in using reproduced absolute address information in a reproducing signal from a disc, and moving an information reading position forcedly. CONSTITUTION:Main information read at the disc 1 with an optical head 3 is led to a photodetection section 4 and photoelectric conversion is done at the section 4. The absolute address information of the main information in a reproducing signal is obtained at an output of an address information detection circuit 6 as a reproduced video signal V at the output of a main signal processing circuit 5. A comparison circuit 16 compares the reproducing absolute address information from the circuit 6 with address information added with one address to the address stored in memories 9, 10 before the unit time. When the both are dissident, a position control signal P is given to the output terminal, a drive section 17 controls the optical head 3 in response to the signal P to move the information reading position of the disc 1.
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公开(公告)号：JP2521905B2
公开(公告)日：1996-08-07
申请号：JP3332186
申请日：1986-02-18
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAGAMI TAMOTSU , YAMAMURA SHINICHI
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公开(公告)号：JPS63197123A
公开(公告)日：1988-08-16
申请号：JP2935187
申请日：1987-02-10
Applicant: SONY CORP
Inventor： SAKO YOICHIRO , YAMAMURA SHINICHI
Abstract: PURPOSE:To reduce the data processing time by generating an error correction code in column and row directions with respect to the data of matrix arrangement, and completing the error correction and error check simultaneously when the error check code is generated. CONSTITUTION:1st and 2nd error correction means 7-9, 10-12 reading the data sequentially from a memory in a row (or column) direction and applying the correction by the 1st and 2nd error correction code, a means 13 generating a check syndrome from the data read out of the memory 1 at the 1st error correction, means 8, 14, 15 applying exclusive OR to the detected error and the error information obtained from the error location for check syndrome, and means 11, 14, 15 applying exclusive OR to the detected error at the 2nd error correction and the error information obtained from the error location for check syndrome are provided. Thus, the number of times of reading data from the memory 1 is decreased by once for check operation to improve the data processing speed.
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公开(公告)号：JPS62192979A
公开(公告)日：1987-08-24
申请号：JP3433886
申请日：1986-02-19
Applicant: SONY CORP
Inventor： YAMAGAMI TAMOTSU , YAMAMURA SHINICHI , SAKO YOICHIRO
Abstract: PURPOSE:To transmit word data of various bit number as a product code of the same format by determining the value of a column so as to constitute one line of an integer word of the relevant bit when transmitting data by forming the product code every specific row and column. CONSTITUTION:The block of the data consisting of (n) bits is constituted every (a) rows X (b) columns and an error correcting code is formed and added in the direction of the row and in the direction of the column with respect to this block data to transmit the data. The data of (m) bits of one word (mnot equal to n) forms the product code by making the one data (n) bits and transmits and is determined so as to have the value of (b) of (nXb)/m=integer. When the product code is formed by making the (n) bits the one word on the data the one word of which is not the (n) bits but the (m) bits, the integer number of words are regularly stored in the one line and the data of the one word does not cross over the two lines.
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