公开(公告)号：US20230335509A1

公开(公告)日：2023-10-19

申请号：US17721271

申请日：2022-04-14

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01F27/28 ,  H01F27/255

CPC classification number: H01L23/645 ,  H01L23/49822 ,  H01L23/29 ,  H01L23/3121 ,  H01L24/16 ,  H01L21/563 ,  H01F27/28 ,  H01F27/255 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate having a top surface including traces and bonding features. There is at least one semiconductor die including a substrate having a semiconductor surface including circuitry electrically connected to bond pads mounted on the bonding features, and at least one inductor coil mounted with a first contact and a second contact that are positioned on the bonding features beyond the semiconductor die including a portion of the inductor over the semiconductor die. There is a dielectric coating on and within the inductor coil, on the semiconductor die, on the traces, and on the bonding features. A magnetic mold compound having magnetic particles and a dielectric material encapsulates the semiconductor die, the inductor, and the dielectric coating.

公开(公告)号：US20230005881A1

公开(公告)日：2023-01-05

申请号：US17364769

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mahmud Chowdhury ,  Hau Nguyen ,  Masamitsu Matsuura ,  Ting-Ta Yen

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.

公开(公告)号：US20230005880A1

公开(公告)日：2023-01-05

申请号：US17364735

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Ashok Surendra Prabhu ,  Hau Nguyen ,  Kurt Edward Sincerbox ,  Makoto Shibuya

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48

Abstract: In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

公开(公告)号：US20220238424A1

公开(公告)日：2022-07-28

申请号：US17719246

申请日：2022-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya Poddar ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

公开(公告)号：US11367699B2

公开(公告)日：2022-06-21

申请号：US17009664

申请日：2020-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Sada ,  Shoichi Iriguchi ,  Genki Yano ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Yi Yan ,  Hau Nguyen

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/495

Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

公开(公告)号：US11183460B2

公开(公告)日：2021-11-23

申请号：US16132906

申请日：2018-09-17

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/538 ,  H01L23/373 ,  H01L21/56 ,  H01L23/498

Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

公开(公告)号：US20200381322A1

公开(公告)日：2020-12-03

申请号：US16996742

申请日：2020-08-18

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Aurora ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

公开(公告)号：US10748827B2

公开(公告)日：2020-08-18

申请号：US16120922

申请日：2018-09-04

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Arora ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

公开(公告)号：US20200161225A1

公开(公告)日：2020-05-21

申请号：US16751088

申请日：2020-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya Poddar ,  Thomas Dyer Bonifield ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/532

Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

公开(公告)号：US20180040420A1

公开(公告)日：2018-02-08

申请号：US15787451

申请日：2017-10-18

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar

IPC: H01F41/04

CPC classification number: H01F41/046 ,  Y10T29/49073

Abstract: In accordance with an embodiment of the application a method of forming an integrated magnetic device is described. A prepreg or core is mounted on a carrier. A winding layer is plated and patterned on the prepreg or core. Vias are plated. The silicon is placed on a die attach pad, ensuring sufficient clearance of die to vias and d/a char. The assembly is laminated and grinded to expose the vias. A 2nd layer of vias is provided by sputtering or plating followed by laminating assembly; and grinding assembly to expose vias. The windings are plated and patterned. A solder mask (SMSK) is applied and assembly finished.