公开(公告)号：WO2016126478A1

公开(公告)日：2016-08-11

申请号：PCT/US2016/015059

申请日：2016-01-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： ZAWODNY, Jason T. ,  WHEELER, Kyle B. ,  MURPHY, Richard C.

IPC: G11C7/06 ,  G11C11/413 ,  G11C11/416

CPC classification number: G06F12/0238 ,  G06F12/0888 ,  G06F15/7821 ,  G06F2212/202 ,  G06F2212/603 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

Abstract translation: 本公开包括与作为用于编程指令的存储器的存储器件相关的装置和方法。 示例性装置包括具有存储器单元阵列和耦合到阵列的感测电路的存储器件。 感测电路包括读出放大器和被配置为实现逻辑运算的计算组件。 耦合到阵列和感测电路的存储器控​​制器被配置为接收包括多个程序指令的指令块。 存储器控制器被配置为将指令块存储在阵列中并检索程序指令以对计算组件执行逻辑运算。

公开(公告)号：WO2015195288A1

公开(公告)日：2015-12-23

申请号：PCT/US2015/032906

申请日：2015-05-28

Applicant: QUALCOMM INCORPORATED

Inventor： AMARILIO, Lior ,  KHAZIN, Alexander

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G11C7/1075 ,  G06F13/287 ,  G06F13/364 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4282 ,  G06F13/4295 ,  G11C7/1036

Abstract: Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation.

Abstract translation: 公开了存储介质之间的时间受限的数据复制。 当电子设备进行实时操作时，在某些时间限制内可能需要将多个数据块从一个存储介质复制到另一个存储介质。 在这方面，数据端口由第一寄存器组的多个寄存器可操作地控制。 多个寄存器在时间限制内从第一寄存器组复制到第二寄存器组，同时数据端口仍然被复制的多个寄存器的控制。 通过在时间限制内复制多个寄存器，可以防止数据端口中的操作中断，并减少与寄存器复制操作相关联的带宽开销。

公开(公告)号：WO2013062561A1

公开(公告)日：2013-05-02

申请号：PCT/US2011/058181

申请日：2011-10-27

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ,  GOLAB, Wojciech ,  PICKETT, Matthew, D. ,  KARP, Alan, H.

Inventor： GOLAB, Wojciech ,  PICKETT, Matthew, D. ,  KARP, Alan, H.

IPC: G11C19/00 ,  G06F12/00

CPC classification number: G11C7/1036 ,  G06F5/00 ,  G06F9/30032 ,  G06F9/30134 ,  G06F9/544 ,  G06F15/7821 ,  G06F2209/521 ,  G11C19/188 ,  G11C19/287

Abstract: A shiftable memory supporting atomic operation employs built-in shifting capability to shift a contiguous subset of data from a first location to a second location within memory during an atomic operation. The shiftable memory includes the memory to store data. The memory has the built-in shifting capability. The shiftable memory further includes an atomic primitive defined on the memory to operate on the contiguous subset.

Abstract translation: 支持原子操作的可移动存储器在原子操作期间使用内置的移位能力来将数据的连续子集从存储器中的第一位置移动到第二位置。 可移动存储器包括用于存储数据的存储器。 内存具有内置的移动功能。 可移位存储器还包括在存储器上定义以在连续子集上操作的原子原语。

公开(公告)号：WO2013015960A2

公开(公告)日：2013-01-31

申请号：PCT/US2012/045510

申请日：2012-07-05

Applicant: MICRON TECHNOLOGY, INC. ,  HENDRICKSON, Nicholas

Inventor： HENDRICKSON, Nicholas

IPC: G11C16/34

CPC classification number: G11C16/26 ,  G11C7/1033 ,  G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C2207/2272 ,  G11C2211/5642

Abstract: Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell.

Abstract translation: 公开了操作存储器设备的装置和方法。 在一种这样的方法中，存储器单元的数据状态的第一部分被确定并从存储器装置转移，同时继续确定相同存储器单元的数据状态的剩余部分。 在至少一种方法中，在第一感测阶段期间确定存储器单元的数据状态，并在存储器单元经历附加感测阶段时传输，以确定存储器单元的数据状态的附加部分。

公开(公告)号：WO2005066975A1

公开(公告)日：2005-07-21

申请号：PCT/US2004/042990

申请日：2004-12-20

Applicant: SANDISK CORPORATION ,  CERNEA, Raul-Adrian ,  LI, Yan

Inventor： CERNEA, Raul-Adrian ,  LI, Yan

IPC: G11C29/00

CPC classification number: G11C7/1036 ,  G11C29/848

Abstract: The present invention presents a non-volatile memory wherein bad columns in the array of memory cells can be removed. According to another aspect of the present invention, substitute redundant columns can replace the removed columns. Both of these processes are performed on the memory in a manner that is externally transparent and, consequently, need not be managed externally by the host or controller to which the memory is attached. An inventory of the bad columns can be maintained on the memory. At power up, the list of bad columns is used to fuse out the bad columns. The memory may also contain a number of redundant columns that can be used to replace the bad columns.

Abstract translation: 本发明提供了一种非易失性存储器，其中可以去除存储器单元阵列中的不良列。 根据本发明的另一方面，替代冗余列可以替代所移除的列。 这些处理都以外部透明的方式在存储器上执行，因此不需要由附加存储器的主机或控制器在外部进行管理。 可以在内存上维护坏列的清单。 上电时，不良列的列表用于对不良列进行融合。 内存还可能包含一些可用于替换不良列的冗余列。

公开(公告)号：WO2004029977A1

公开(公告)日：2004-04-08

申请号：PCT/US2003/029141

申请日：2003-09-17

Applicant: SANDISK CORPORATION

Inventor： CERNEA, Raul-Adrian

IPC: G11C7/10

CPC classification number: G11C19/00 ,  G11C7/1036 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5642

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. In one aspect, data latches associated with the multiple read/write circuits are I/O enabled and coupled in a compact manner for storage and serial transfer. They are implemented by one or more chain of link modules, which can selectively behave as inverters or latches. A method enables the use of a minimum number of link modules by cycling data between a set of master link modules and a substantially smaller set of slave link modules.

Abstract translation: 能够并行读取和写入大量存储器单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。 在一个方面，与多个读/写电路相关联的数据锁存器是以紧凑的方式启用和耦合的I / O进行存储和串行传输。 它们由一个或多个链路链路模块实现，链路模块可以选择性地表现为反相器或锁存器。 一种方法能够通过在一组主链路模块和较小的一组从属链路模块之间循环数据来使用最少数量的链路模块。

公开(公告)号：WO99039909A2

公开(公告)日：1999-08-12

申请号：PCT/US1999/002901

申请日：1999-02-10

IPC: B41J2/01 ,  B41J2/045 ,  B41J2/05 ,  B41J2/055 ,  B41J2/125 ,  B41J2/175 ,  B41J25/34 ,  B41J29/38 ,  G11C7/10 ,  G11C8/10 ,  G11C16/02 ,  B41J

CPC classification number: B41J2/17546 ,  B41J2/04541 ,  B41J2/04563 ,  B41J2/0458 ,  B41J2/17526 ,  B41J25/34 ,  B41J2202/17 ,  G11C7/1036 ,  G11C8/10

Abstract: An ink jet print head identification system for providing print head identifying information to the electronics of an ink jet printer includes one or more parallel load, serial out, dynamic shift registers integrated into a print head chip having a plurality of address lines interconnecting the printer electronics and the print head electronics. The memory input of each shift register is electrically connected to a memory matrix that supplies digital bits of information to the shift register in response to receiving a decode signal function from the printer electronics. In a preferred embodiment, two of the address lines provide each of the registers with successive sequential clock signals to serially shift the bit of information received from the shift register's corresponding memory matrix to an output line where the print head identifying information is read by the printer electronics. Embodiments of the invention may employ any number of shift registers and memory matrices independent of the number of available address lines.

Abstract translation: 一种用于向喷墨打印机的电子设备提供打印头识别信息的喷墨打印头识别系统包括集成到打印头芯片中的一个或多个并行负载串行输出动态移位寄存器，该打印头芯片具有多个地址线， 和打印头电子元件。 每个移位寄存器的存储器输入电连接到存储矩阵，该存储器矩阵响应于从打印机电子器件接收解码信号功能而将数字位信息提供给移位寄存器。 在优选实施例中，两个地址线向每个寄存器提供连续的顺序时钟信号，以将从移位寄存器的相应存储矩阵接收到的信息的位串行移位到打印头识别信息被打印机读取的输出行 电子产品。 本发明的实施例可以采用独立于可用地址线的数量的任意数量的移位寄存器和存储器矩阵。

公开(公告)号：WO2017201050A1

公开(公告)日：2017-11-23

申请号：PCT/US2017/032906

申请日：2017-05-16

Applicant: MINATI, Ludovico ,  FANDRICH, Mickey Lee

Inventor： MINATI, Ludovico ,  FANDRICH, Mickey Lee

IPC: C12Q1/68 ,  G06F19/22 ,  G01N33/48

CPC classification number: G16B30/00 ,  G06F5/01 ,  G06F13/1668 ,  G06F13/4282 ,  G06F15/7821 ,  G06F2213/0026 ,  G06F2213/0042 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/41 ,  G11C19/00 ,  G11C19/184 ,  G11C19/287 ,  H03K19/21

Abstract: A computer system and method for sequencing deoxyribonucleic acid (DNA), to determine the order of the different nucleotides in a genomic sequence or sequence fragment. An alignment system employs a direct "brute force" Hamming distance calculation between a read sequence and a reference genome. The alignment system is configured to compare directly a set of DNA fragments to a reference genome in a short period, and with the higher probability of accuracy than similar comparison systems given the same number of clock cycles. Each DNA fragment is compared with a reference genome for the entire length of the latter using arrangements of memory cells for storing read sequences and inverse complements of the read sequences, shift registers for streaming the reference genome, and circuitry for calculating and summing the distance between the reference, the read sequence, and the inverse complement in parallel. Both digital and analog implementations are described.

Abstract translation: 测定脱氧核糖核酸（DNA）的计算机系统和方法，以确定基因组序列或序列片段中不同核苷酸的顺序。 对准系统采用直接的“强力” 阅读序列和参考基因组之间的汉明距离计算。 对比系统被配置为在短时间段内将一组DNA片段直接与参考基因组进行比较，并且与给定相同数量的时钟周期的类似比较系统相比，其准确度更高。 使用用于存储读取序列的读取序列和反向互补序列的存储器单元的布置，用于流式传输参考基因组的移位寄存器以及用于计算和累加之间的距离的电路来将每个DNA片段与参考基因组进行比较 参考，读取序列和反向并行补码。 描述了数字和模拟实现。

公开(公告)号：WO2013130109A1

公开(公告)日：2013-09-06

申请号：PCT/US2012/027607

申请日：2012-03-02

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY L.P. ,  KARP, Alan, H.

Inventor： KARP, Alan, H.

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F12/023 ,  G06F3/0608 ,  G06F17/30135 ,  G06F2212/161 ,  G06F2212/70 ,  G11C7/1036 ,  G11C13/0007 ,  G11C19/00 ,  G11C19/28

Abstract: Shiftable memory that supports defragmentation includes a memory having built- in shifting capability, and a memory defragmenter to shift a page of data representing a contiguous subset of data stored in the memory from a first location to a second location within the memory to be adjacent to another page of stored data. A method of memory defragmentation includes defining an array in memory cells of the shiftable memory and performing a memory defragmentation using the built-in shifting capability of the shiftable memory to shift a data page stored in the array.

Abstract translation: 支持碎片整理的可移动存储器包括具有内置移位能力的存储器，以及存储器碎片整理器，用于将表示存储在存储器中的数据的连续子集的数据页从第一位置移动到与存储器相邻的第二位置 存储数据的另一页。 一种内存碎片整理方法包括：在可移位存储器的存储器单元中定义一个阵列，并使用可移位存储器的内置移位能力执行存储器碎片整理，以移位存储在阵列中的数据页。

公开(公告)号：WO2010045029A1

公开(公告)日：2010-04-22

申请号：PCT/US2009/059129

申请日：2009-09-30

Applicant: MICRON TECHNOLOGY, INC. ,  NOYES, Harold B ,  JURENKA, Mark ,  HUGGINS, Gavin

Inventor： NOYES, Harold B ,  JURENKA, Mark ,  HUGGINS, Gavin

IPC: G06F9/30 ,  G06F9/318

CPC classification number: G11C7/1036 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/34 ,  G06F12/0615 ,  G06F2212/656

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

Abstract translation: 提供了系统和方法来管理对寄存器的访问。 在一个实施例中，系统可以包括处理器和多个寄存器。 处理器和多个寄存器可以集成到单个设备中，或者可以在单独的设备中。 多个寄存器可以包括可由处理器直接访问的第一组寄存器和不能由处理器直接访问的第二组寄存器。 然而，第二组寄存器可以由处理器经由第一组寄存器间接访问。 在一个实施例中，第一组寄存器可以包括用于从第二组寄存器中选择寄存器组的寄存器和用于选择寄存器组中的特定地址的寄存器，以允许处理器间接访问寄存器组的寄存器 第二集