SOUNDWIRE-BASED EMBEDDED DEBUGGING IN AN ELECTRONIC DEVICE
    1.
    发明申请
    SOUNDWIRE-BASED EMBEDDED DEBUGGING IN AN ELECTRONIC DEVICE 审中-公开
    基于声音的嵌入式调试在电子设备中

    公开(公告)号:WO2018026559A1

    公开(公告)日:2018-02-08

    申请号:PCT/US2017/043514

    申请日:2017-07-24

    Abstract: SoundWire-based embedded debugging in an electronic system is provided. In this regard, in one aspect, a SoundWire slave circuit receives a SoundWire data input signal over a SoundWire bus including two physical wires. The SoundWire data input signal includes a plurality of debug configuration bits in assigned SoundWire bitslots. The SoundWire slave circuit generates a plurality debug input bits required for debugging the SoundWire slave circuit based on the debug configuration bits received in the assigned SoundWire bitslots. In another aspect, the SoundWire slave circuit returns a SoundWire data output signal, which includes a debug output bit in an assigned SoundWire bitslot, over the SoundWire bus. By receiving debugging configurations and returning debugging results over the SoundWire bus, it is possible to debug the SoundWire slave circuit with a reduced number of physical pins, thus helping to reduce the overall pin count and footprint of the electronic device.

    Abstract translation:

    提供了基于SoundWire的电子系统嵌入式调试。 在这方面,在一个方面,SoundWire从电路通过包括两条物理电线的SoundWire总线接收SoundWire数据输入信号。 SoundWire数据输入信号在分配的SoundWire位中包含多个调试配置位。 SoundWire从电路根据指定的SoundWire位中接收到的调试配置位,生成调试SoundWire从电路所需的多个调试输入位。 另一方面,SoundWire从电路通过SoundWire总线返回一个SoundWire数据输出信号,其中包括一个指定的SoundWire位槽中的调试输出位。 通过接收调试配置并通过SoundWire总线返回调试结果,可以通过减少物理引脚数量来调试SoundWire从电路,从而有助于减少电子设备的总体引脚数量和占用空间。

    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES
    2.
    发明申请
    MULTI-CHANNEL AUDIO ALIGNMENT SCHEMES 审中-公开
    多声道音频对准方案

    公开(公告)号:WO2016076989A1

    公开(公告)日:2016-05-19

    申请号:PCT/US2015/054861

    申请日:2015-10-09

    Abstract: Multi-channel audio alignment schemes are disclosed. One aspect of the present disclosure provides for accumulation of audio samples across multiple related audio channels at an audio source. Related audio channels indicate their interrelatedness, and when all the related audio channels have data to transmit, the source releases the data onto the time slots of the Serial Low-power Inter-chip Media Bus (SLIMbus), such that the related audio channels are within a given segment window of the time slot. This accumulation is repeated at the boundary of every segment window. Similarly, accumulation may be performed at the audio sink. Components within the audio sink may only read received data if status signals from all related sinks indicate that predefined thresholds have been reached. By providing such accumulation options, audio fidelity is maintained across multiple audio data channels.

    Abstract translation: 公开了多声道音频对准方案。 本公开的一个方面提供了音频源在多个相关音频通道上的累积。 相关的音频通道表示它们的相互关联性,当所有相关的音频通道都具有要发送的数据时,源将数据释放到串行低功率芯片间媒体总线(SLIMbus)的时隙上,使得相关的音频通道 在时隙的给定段窗口内。 在每个分段窗口的边界处重复该累积。 类似地,可以在音频接收器处执行累加。 音频接收器中的组件只能从所有相关接收器的状态信号指示已达到预定义的阈值时才读取接收到的数据。 通过提供这种累积选项,可以在多个音频数据通道之间保持音频保真度。

    TIME-CONSTRAINED DATA COPYING BETWEEN STORAGE MEDIA
    3.
    发明申请
    TIME-CONSTRAINED DATA COPYING BETWEEN STORAGE MEDIA 审中-公开
    存储介质之间的时间限制数据复制

    公开(公告)号:WO2015195288A1

    公开(公告)日:2015-12-23

    申请号:PCT/US2015/032906

    申请日:2015-05-28

    Abstract: Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation.

    Abstract translation: 公开了存储介质之间的时间受限的数据复制。 当电子设备进行实时操作时,在某些时间限制内可能需要将多个数据块从一个存储介质复制到另一个存储介质。 在这方面,数据端口由第一寄存器组的多个寄存器可操作地控制。 多个寄存器在时间限制内从第一寄存器组复制到第二寄存器组,同时数据端口仍然被复制的多个寄存器的控制。 通过在时间限制内复制多个寄存器,可以防止数据端口中的操作中断,并减少与寄存器复制操作相关联的带宽开销。

    MULTI-CHANNEL AUDIO COMMUNICATION IN A SERIAL LOW-POWER INTER-CHIP MEDIA BUS (SLIMBUS) SYSTEM

    公开(公告)号:EP3189442B1

    公开(公告)日:2018-10-31

    申请号:EP15763748.9

    申请日:2015-09-02

    CPC classification number: G06F3/162 G06F13/28 G06F13/287 G06F13/4282 H04S3/008

    Abstract: Multi-channel audio communication in a Serial Low-power Inter-chip Media Bus (SLIMbus) system is disclosed. In this regard, in one aspect, a multi-channel output port is provided in a SLIMbus system. The multi-channel output port receives an audio stream from an audio source (e.g., a storage medium) via a direct memory access (DMA) pipe and distributes the audio stream to multiple receiving ports (e.g., speakers) over multiple data channels, all connected to the single multi-channel output port. In another aspect, a multi-channel input port is provided in a SLIMbus system. The multi-channel input port connects to multiple data channels from multiple distributing ports (e.g., microphones). By providing the multi-channel output port and/or the multi-channel input port in a SLIMbus system, it is possible to support multiple data channels with a single DMA pipe, thus improving implementation flexibilities and efficiencies of the SLIMbus system.

    TIME-CONSTRAINED DATA COPYING BETWEEN STORAGE MEDIA
    5.
    发明公开
    TIME-CONSTRAINED DATA COPYING BETWEEN STORAGE MEDIA 审中-公开
    存储介质之间的时间约束数据复制

    公开(公告)号:EP3158458A1

    公开(公告)日:2017-04-26

    申请号:EP15732084.7

    申请日:2015-05-28

    Abstract: Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation.

    Abstract translation: 公开了存储介质之间时间受限的数据复制。 当电子设备进行实时操作时,可能需要在一定的时间限制内将多个数据块从一个存储介质复制到另一个存储介质。 就这一点而言,数据端口由第一寄存器组的多个寄存器可操作地控制。 多个寄存器在时间限制内从第一寄存器组复制到第二寄存器组,并且数据端口保持在被复制的多个寄存器的控制下。 通过在时间限制内复制多个寄存器,可以防止数据端口中的操作中断并减少与寄存器复制操作相关的带宽开销。

    I2C BUS ARCHITECTURE USING SHARED CLOCK AND DEDICATED DATA LINES

    公开(公告)号:WO2022235348A1

    公开(公告)日:2022-11-10

    申请号:PCT/US2022/021977

    申请日:2022-03-25

    Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

    TUNNELING OVER UNIVERSAL SERIAL BUS (USB) SIDEBAND CHANNEL

    公开(公告)号:WO2022093418A1

    公开(公告)日:2022-05-05

    申请号:PCT/US2021/050544

    申请日:2021-09-15

    Abstract: Tunneling over Universal Serial Bus (USB) sideband channel systems and methods provide a way to tunnel I2C transactions between a master and slaves over USB 4.0 sideband channels. More particularly, a slave address table lookup (SATL) circuit is added to a host circuit. Signals from an I2C bus are received at the host, and any address associated with a destination is translated by the SATL. The translated address is passed to a low-speed interface associated with a sideband channel in the host circuit. Signals received at the low-speed interface are likewise reverse translated in the SATL and then sent out through the I2C bus. In this fashion, low-speed I2C signals may be routed over the sideband channel through the low-speed sideband interface portion of the USB interface.

    URGENT IN-BAND INTERRUPTS ON AN I3C BUS
    8.
    发明申请

    公开(公告)号:WO2020060838A1

    公开(公告)日:2020-03-26

    申请号:PCT/US2019/050830

    申请日:2019-09-12

    Abstract: Systems, methods, and apparatus are described that enable communication of inband reset signals over an I3C serial bus. A method performed at a slave device includes driving a data line of the I3C serial bus from a high state to a low state before a first clock pulse is received from a clock line of the I3C serial bus after a start condition has been provided on the I3C serial bus, where driving the data line from the high state to the low state produces an initial pulse on the data line, transmitting one or more additional pulses on the data line before the first clock pulse is transmitted on the clock line, and driving the data line low until a rising edge of the first clock pulse is detected on the clock line after each of the plurality of additional pulses has been successfully transmitted on the data line.

    PHASE ALIGNMENT IN AN AUDIO BUS
    9.
    发明申请

    公开(公告)号:WO2019177704A1

    公开(公告)日:2019-09-19

    申请号:PCT/US2019/015805

    申请日:2019-01-30

    Abstract: Exemplary aspects of the present disclosure assist in phase alignment for systems having multiple audio sources. For example, in a system having plural microphones, phase alignment may also be assisted by sampling the microphones at the appropriate time relative to when the samples are placed on the audio bus. Further, phase shifts between audio samples are reduced or eliminated by keeping a sample delay constant for samples from the same microphone. Such manipulation of the audio samples reduces phase shifts which reduces the likelihood of an audio artifact capable of being detected by the human ear and thus improves consumer experience.

    PROVIDING ZERO-OVERHEAD FRAME SYNCHRONIZATION USING SYNCHRONIZATION STROBE POLARITY FOR SOUNDWIRE EXTENSION BUSES

    公开(公告)号:WO2019045973A1

    公开(公告)日:2019-03-07

    申请号:PCT/US2018/045739

    申请日:2018-08-08

    Abstract: Providing zero-overhead frame synchronization using synchronization strobe polarity for SOUNDWIRE Extension buses is disclosed. In one aspect, a downstream-facing interface (DFI) device determines a polarity of a next synchronization strobe of a bitstream based on a value of a next frame synchronization pattern, and adjusts the next synchronization strobe of the bitstream to comprise a signal transition corresponding to the polarity. The processor-based DFI device then transmits the bitstream containing the next synchronization strobe (e.g., via a SOUNDWIRE Extension bus, such as a SOUNDWIRE-XL or SOUNDWIRE-NEXT bus, to one or more upstream-facing interface (UFI) devices). In another aspect, a processor-based UFI device receives the bitstream, and detects the encoded polarity of the synchronization strobe. The processor-based UFI device reconstructs the frame synchronization pattern based on the polarity of the synchronization strobe, and performs frame synchronization based on the frame synchronization pattern.

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