Abstract:
A phase-locked-loop circuit includes an oscillator having switched capacitors that are selectively coupled to a positive feedback path of the oscillator in a coarse frequency error correction mode of operation. When the frequency error is small, the circuit operates in a fine error correction mode without varying the selection of the switched reactive elements.
Abstract:
Controllable quadrature oscillator having a pair of oscillator outputs (01, 02) for supplying a pair of phase quadrature oscillator signals, and a cascade circuit of two quadrature sections (A, B), which circuit is incorporated in a regenerative loop, one (B) of the two quadrature sections being arranged between the two oscillator outputs and realising a 90 o phase shift in the regenerative state of the loop. In order to increase the frequency control range of such a controllable quadrature oscillator and to provide the possibility of integration, at least the said quadrature section comprises a cascade circuit of two stages (B1, B2) arranged in a signal path between an input terminal and an output terminal, one stage (B1) comprising a first amplifier having a low-pass characteristic and the other stage comprising a second amplifier (B2) having a low-pass characteristic, said second amplifier having a feedback path, and the gain of at least one of the two amplifiers being controllable for controlling the frequency of the pair of phase quadrature oscillator signals.
Abstract:
A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
Abstract:
A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO (222) includes a parallel LC circuit (228) having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.
Abstract:
In a phase-lock-loop circuit a frequency detector measures a frequency error between an oscillatory signal and a synchronizing signal in alternate horizontal line periods for generating a frequency error indicative signal. The frequency error indicative signal is applied to an oscillator for correcting the frequency error in other alternate horizontal line periods in a manner to prevent frequency error measurement and correction from occurring in the same horizontal line period.
Abstract:
A coplanar waveguide based microwave monolithic integrated circuit (MMIC) oscillator chip (14) has an active oscillator element (16) and a resonant capacitor (18) formed thereon and is flip-chip mounted on a dielectric substrate (12). A resonant inductor (22) is formed on the substrate (12) and interconnected with the resonant capacitor (18) to form a high Q-factor resonant circuit for the oscillator (10). The resonant inductor (22) includes a shorted coplanar waveguide section (24) consisting of first and second ground strips (24b, 24c), and a conductor strip (24a) extending between the first and second ground strips (24b, 24c) in parallel relation thereto and being separated therefrom by first and second spaces (26a, 26b), respectively. A shorting strip (24d) electrically interconnects adjacent ends of the conductor strip (24a) and first and second ground strips (24b, 24c), respectively. A dielectric film (34) may be formed over at least adjacent portions of the conductor strip (24a) and first and second ground strips (24b, 24c). The resonant inductor (22) is adjusted to provide a predetermined resonant frequency for the oscillator (10) by using a laser to remove part of the dielectric film (34) in the first and second spaces (26a, 26b) for fine adjustment, and/or to remove part of the shorting strip (24d) at the ends of the first and second spaces (26a, 26b) for coarse adjustment.
Abstract:
A clamped linear transconductance amplifier path, consisting essentially of a current clamp (M23) merged in a linear transconductance amplifier (M23, M21,M22) path, is used in a triple-input, single-output transconductor (200). In a balanced transconductor in CMOS technology, this clamped linear transconductance amplifier path is formed by a p-channel MOS transistor (M23) separately connected in series with each of a matched pair of p-channel MOS transistors (M21, M22). The clamped linear transconductance amplifier path, together with two other transconductance paths (M15-M20; M9-M14), can be interconnected to form the input side of the triple-input, single-output transconductor (200). By summing and integrating the outputs of the input side of the triple-input transconductor (200), the output (VOUT,P and VOUT,N) of the output side of the transconductor can be formed. By feeding back this output to the input side of the transconductor (200), an oscillator can obtained.
Abstract:
A clamped linear transconductance amplifier path, consisting essentially of a current clamp (M23) merged in a linear transconductance amplifier (M23, M21,M22) path, is used in a triple-input, single-output transconductor (200). In a balanced transconductor in CMOS technology, this clamped linear transconductance amplifier path is formed by a p-channel MOS transistor (M23) separately connected in series with each of a matched pair of p-channel MOS transistors (M21, M22). The clamped linear transconductance amplifier path, together with two other transconductance paths (M15-M20; M9-M14), can be interconnected to form the input side of the triple-input, single-output transconductor (200). By summing and integrating the outputs of the input side of the triple-input transconductor (200), the output (VOUT,P and VOUT,N) of the output side of the transconductor can be formed. By feeding back this output to the input side of the transconductor (200), an oscillator can obtained.
Abstract:
Bei einem abstimmbaren Resonanzverstärker oder Oszillator sind eine erste (DS1) und eine zweite (DS2) Differenzstufe vorgesehen und die erste Differenzstufe wird von einer ersten Stromquelle (I1) und die zweite Differenzstufe wird von einer zweiten Stromquelle (I2) gespeist. Die Ausgangsanschlußpaare (A1,A2;A3,A4) der ersten und zweiten Differenzstufe sind mit je einem Kondensator (C1;C2) beschaltet und die Ausgangsanschlüsse der ersten und zweiten Differenzstufe sind mit je einer dritten bis sechsten Stromquelle (I3,I4;I5,I6) verbunden. Der Eingang (E1, E2) der ersten Differenzstufe ist mit dem Ausgang der zweiten Differenzstufe und der Eingang (E3, E4) der zweiten Differenzstufe ist mit dem Ausgang der ersten Differenzstufe verbunden. Die Eingänge der fünften und sechsten Stromquelle sind über ein ersten Koppelglied (T9) mit dem Einspeisepunkt (B1) der ersten Stromquelle und die Eingänge der dritten und vierten Stromquelle sind über ein zweites Koppelglied (T10) mit dem Einspeisepunkt (B2) der zweiten Stromquelle verbunden.