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    METAL-OXIDE-METAL CAPACITORS WITH BAR VIAS
    61.
    发明申请
    METAL-OXIDE-METAL CAPACITORS WITH BAR VIAS 审中-公开
    METAL-OXIDE-METAL电容器与酒吧VIAS

    公开(公告)号：WO2010042542A3

    公开(公告)日：2010-07-15

    申请号：PCT/US2009059729

    申请日：2009-10-06

    Applicant: ALTERA CORP ,  SARDANA CHARU ,  RATNAKUMAR ALBERT ,  JENSEN BRADLEY ,  WATT JEFFREY T

    Inventor： SARDANA CHARU ,  RATNAKUMAR ALBERT ,  JENSEN BRADLEY ,  WATT JEFFREY T

    IPC: H01L27/108 ,  H01L27/04

    CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Metal-oxide-metal capacitors with bar vias are provided for integrated circuits. The capacitors may be formed in the interconnect layers of integrated circuits. Stacked bar vias and metal lines in the interconnect layers may be connected to form conductive vertical plates that span multiple interconnect layers. The capacitors with bar vias may be formed by placing multiple vertical plates formed from stacked bar vias and metal lines parallel to each other, alternating the polarity of adjacent vertical parallel plates to form multiple parallel plate capacitors. The parallel plates may be interconnected to form first and second terminals in a capacitor.

    Abstract translation: 为集成电路提供带条形过孔的金属氧化物金属电容器。 电容器可以形成在集成电路的互连层中。 互连层中的堆叠条形过孔和金属线可以连接以形成跨越多个互连层的导电垂直板。 具有条形过孔的电容器可以通过放置由堆叠条形过孔和金属线形成的多个垂直板彼此平行，交替相邻垂直平行板的极性以形成多个平行板电容器来形成。 平行板可以互连以形成电容器中的第一和第二端子。

    PROCESS/DESIGN METHODOLOGY TO ENABLE HIGH PERFORMANCE LOGIC AND ANALOG CIRCUITS USING A SINGLE PROCESS
    64.
    发明申请
    PROCESS/DESIGN METHODOLOGY TO ENABLE HIGH PERFORMANCE LOGIC AND ANALOG CIRCUITS USING A SINGLE PROCESS 审中-公开
    工艺/设计方法使用单一工艺实现高性能逻辑和模拟电路

    公开(公告)号：WO2010039444A2

    公开(公告)日：2010-04-08

    申请号：PCT/US2009057271

    申请日：2009-09-17

    Applicant: ALTERA CORP ,  XIANG QI ,  RATNAKUMAR ALBERT ,  TUNG JEFFREY XIAOQI ,  DING WEIQI

    Inventor： XIANG QI ,  RATNAKUMAR ALBERT ,  TUNG JEFFREY XIAOQI ,  DING WEIQI

    IPC: H01L27/088 ,  H01L21/265

    CPC classification number: G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

    Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

    Abstract translation: 提出了一种使用正向偏置和改进的混合信号处理的电路设计来提高模拟电路性能的方法。 定义了由多个NMOS和PMOS晶体管组成的电路。 NMOS晶体管的体端耦合到第一电压源并且PMOS晶体管的体端耦合到第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的本体端子并且将第二电压源施加到每个选定的PMOS晶体管的本体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的本体端子提供正向和反向偏置。

    AUTOMATIC CALIBRATION IN HIGH-SPEED SERIAL INTERFACE RECEIVER CIRCUITRY
    65.
    发明申请
    AUTOMATIC CALIBRATION IN HIGH-SPEED SERIAL INTERFACE RECEIVER CIRCUITRY 审中-公开
    高速串行接口电路中的自动校准

    公开(公告)号：WO2010039232A2

    公开(公告)日：2010-04-08

    申请号：PCT/US2009005396

    申请日：2009-09-29

    Applicant: ALTERA CORP ,  SHUMARAYEV SERGEY ,  WONG WILSON

    Inventor： SHUMARAYEV SERGEY ,  WONG WILSON

    IPC: H04L27/01

    CPC classification number: H04L25/03885 ,  H04B3/04 ,  H04L1/205 ,  H04L25/03019

    Abstract: Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.

    Abstract translation: 用于接收串行数据信号（例如，高速串行数据信号）的电路包括用于产生串行数据信号的均衡版本的可调均衡器电路。 均衡器电路可以包括可控可变DC增益和可控可变AC增益。 该电路还可以包括用于分别产生指示均衡版本的眼睛的高度和宽度的第一和第二输出信号的眼高和眼宽度监视器电路。 第一输出信号可以用于控制均衡器电路的DC增益，第二输出信号可以用于控制均衡器电路的AC增益。

    METHOD AND APPARATUS FOR ENHANCING THE TRIGGERING OF AN ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    66.
    发明申请
    METHOD AND APPARATUS FOR ENHANCING THE TRIGGERING OF AN ELECTROSTATIC DISCHARGE PROTECTION DEVICE 审中-公开
    用于增强静电放电保护装置的触发的方法和装置

    公开(公告)号：WO2010030968A2

    公开(公告)日：2010-03-18

    申请号：PCT/US2009056785

    申请日：2009-09-14

    Applicant: ALTERA CORP ,  GALLERANO ANTONIO ,  WATT JEFFREY T

    Inventor： GALLERANO ANTONIO ,  WATT JEFFREY T

    IPC: H01L23/60

    CPC classification number: H01L27/0277 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electrostatic discharge (ESD) protection circuit for protecting a semiconductor device that includes a metal oxide semiconductor field effect transistor (MOSFET) providing a first path from a source of an electrostatic charge to ground. The ESD protection circuit also includes an NPN bipolar transistor providing a second path from the source of the electrostatic charge to ground. The ESD protection circuit also includes a regulation component coupled in series to a base of the NPN bipolar transistor to provide an amount of resistance when the semiconductor device is off and to provide a reduced amount of resistance when the semiconductor device is on.

    Abstract translation: 一种用于保护半导体器件的静电放电（ESD）保护电路，其包括提供从静电电荷源到地的第一路径的金属氧化物半导体场效应晶体管（MOSFET）。 ESD保护电路还包括提供从静电电荷源到地的第二路径的NPN双极晶体管。 ESD保护电路还包括与NPN双极晶体管的基极串联耦合的调节部件，以在半导体器件关断时提供一定量的电阻，并且当半导体器件导通时提供减小的电阻量。

    PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION
    67.
    发明申请
    PLD ARCHITECTURE OPTIMIZED FOR 10G ETHERNET PHYSICAL LAYER SOLUTION 审中-公开
    针对10G以太网物理层解决方案优化的PLD架构

    公开(公告)号：WO2009126267A3

    公开(公告)日：2010-01-14

    申请号：PCT/US2009002188

    申请日：2009-04-07

    Applicant: ALTERA CORP ,  CHAN ALLEN ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  DING WEIQI

    Inventor： CHAN ALLEN ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  DING WEIQI

    IPC: H04L12/56

    CPC classification number: H04L49/30 ,  H04L49/352

    Abstract: An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.

    Abstract translation: 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10吉比特以太网（10GbE）收发器电路。 可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。 该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。 将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

    VOLATILE MEMORY ELEMENTS WITH ELEVATED POWER SUPPLY LEVELS FOR PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS
    68.
    发明申请
    VOLATILE MEMORY ELEMENTS WITH ELEVATED POWER SUPPLY LEVELS FOR PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS 审中-公开
    具有可编程逻辑器件集成电路的高电压电平的易失性存储器元件

    公开(公告)号：WO2007061667A3

    公开(公告)日：2008-01-03

    申请号：PCT/US2006044014

    申请日：2006-11-10

    Applicant: ALTERA CORP ,  LIU LIN-SHIH ,  CHAN MARK T ,  DO TOAN D

    Inventor： LIU LIN-SHIH ,  CHAN MARK T ,  DO TOAN D

    IPC: G11C5/14 ,  G11C7/00 ,  G11C7/10 ,  G11C11/00 ,  H01L25/00 ,  H03K19/177

    CPC classification number: G11C5/14 ,  G05F1/465 ,  G11C11/413 ,  H03K19/1776 ,  H03K19/17784 ,  H03K19/17792

    Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals . The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level .

    Abstract translation: 提供具有易失性存储元件的集成电路。 存储元件产生输出信号。 集成电路可以是包含可编程逻辑逻辑的可编程逻辑器件集成电路，包括具有栅极的晶体管。 核心逻辑使用由核心逻辑正电源电压和核心逻辑地电压定义的核心逻辑电源电源供电。 当加载配置数据时，存储器元件产生施加到核心逻辑中的晶体管的栅极的输出信号以定制可编程逻辑器件。 存储元件由存储元件正电源电压和存储元件接地电源电压限定的存储元件电源电平供电。 存储元件电源电平相对于核心逻辑电源电平升高。

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