SELECTIVE RECEIVER FOR EACH PROCESSOR IN A MULTIPLE PROCESSOR SYSTEM
    61.
    发明申请
    SELECTIVE RECEIVER FOR EACH PROCESSOR IN A MULTIPLE PROCESSOR SYSTEM 审中-公开
    多处理器系统中的每个处理器的选择接收器

    公开(公告)号:WO1989003565A1

    公开(公告)日:1989-04-20

    申请号:PCT/US1988001283

    申请日:1988-04-20

    CPC classification number: G06F15/17

    Abstract: Circuitry, and associated methodology, in a parallel processing system (50) for sharing the address space among a plurality of autonomous processors (110, 210, 310) communicating over a common bus provides an efficient, non-destructive data transfer and storage environment. This is effected by augmenting each processor with buffer means (e.g. 140) for storing data received off the bus, and means (e.g. 120, 130) for selectively enabling the buffer means to accept those segments of data having addresses allocated to the given processor. To avoid overwriting of data during bus conflicts, the buffer means are arranged to store data on a first-in, first-out basis and to control the processing states and data transfer in correspondance to respective bus and processor states.

    Abstract translation: 在用于在通过公共总线通信的多个自治处理器(110,210,310)中共享地址空间的并行处理系统(50)中的电路和相关方法提供了一种有效的,非破坏性的数据传输和存储环境。 这通过用用于存储从总线接收的数据的缓冲器装置(例如140)来增强每个处理器以及用于选择性地使得缓冲器装置接受具有分配给给定处理器的地址的那些数据段的装置(例如,120,130)来实现。 为了避免在总线冲突期间覆盖数据,缓冲器装置被安排为以先入先出的方式存储数据,并且控制对应于各个总线和处理器状态的处理状态和数据传输。

    PARALLEL PROCESSING STATE ALIGNMENT
    62.
    发明申请
    PARALLEL PROCESSING STATE ALIGNMENT 审中-公开
    并行处理状态对齐

    公开(公告)号:WO1988004810A1

    公开(公告)日:1988-06-30

    申请号:PCT/US1987001750

    申请日:1987-07-23

    CPC classification number: G06F9/4806 G06F9/54 G06F15/17

    Abstract: Circuitry, and associated methodology, in a parallel processing environment for aligning the various processing states of the autonomous processors (100, 1100, 2100) communicating over a common bus (301) assures that the order of execution and alignment of processing states is preserved across processors. This is effected by augmenting each processor with a state alignment network (50, 1050, 2050) for inhibiting, within one interval of the global reference generator (110), generation of global reference signals. The reference generator is restarted only after all processing is completed in the order required by the allocation of tasks among the processors. To provide maximal efficiency, the state alignment network (50, 1050, 2050) incorporates an arrangement (300, 1300, 2300) to detect periods of delay between scheduled tasks and to automatically advance to the next immediate state requiring processing.

    ENCODING AND DECODING SIGNALS FOR TRANSMISSION OVER A MULTI-ACCESS MEDIUM
    63.
    发明申请
    ENCODING AND DECODING SIGNALS FOR TRANSMISSION OVER A MULTI-ACCESS MEDIUM 审中-公开
    编码和解码用于多媒体传输的信号

    公开(公告)号:WO1987006412A1

    公开(公告)日:1987-10-22

    申请号:PCT/US1986002596

    申请日:1986-12-02

    CPC classification number: H04L7/08

    Abstract: An encoder (400) method for processing an input data signal to produce binary coded data frames and to provide for synchronized, high-speed operation partitions the incoming data into contiguous frames composed of a plurality of bit position. For each frame, a synchronizing signal comprising a pulse in the first bit position and no pulse in the midpoint bit position is propagated over the channel (101, 140, 161). Any station (110, 120 or 130) gaining access to the channel propagates its data samples in the remaining positions in each frame. Thus, the channel signal includes a component which is a subharmonic of the bit rate and this subharmonic is used to derive a synchronizing signal in a decoder (200). The decoder method for detecting the samples in the contiguous frames includes the steps of processing the synchronizing signal to produce signals at both the frame and bit rates and extracting a sampling signal in correspondance to the locations of the data samples in the frames. In order to achieve a preselected end-to-end transmission rate in the overall system, the rate of the signal propagated between encoder (400) and decoder (200) is increased to compensate for the interleaved synchronizing signal.

    SEMICONDUCTOR LASER FABRICATION
    64.
    发明申请
    SEMICONDUCTOR LASER FABRICATION 审中-公开
    半导体激光制造

    公开(公告)号:WO1987006398A1

    公开(公告)日:1987-10-22

    申请号:PCT/US1987000279

    申请日:1987-02-06

    CPC classification number: B82Y20/00 H01S5/34306 H01S5/34313

    Abstract: A method of making a semiconductor laser from a gallium arsenide substrate of a first conductivity type by depositing a first layer of semiconductor material having the composition AlxGal-xAs of first conductivity type on the substrate and a thin second layer of semiconductor material for quantum confinement having the composition InyGa1-yAs on the first layer. This layer experiences sufficient strain in the semiconductor structure so as to minimize the threshold current density. The device is completed by depositing a third layer of semiconductor material having the composition AlxGal-xAs and of second conductivity type on the second layer, and depositing a fourth layer of semiconductor material having the composition GaAs and of second conductivity type on the third layer.

    Abstract translation: 一种通过在衬底上沉积具有第一导电类型的组成Al x Ga 1-x As的第一半导体材料层和用于量子限制的薄的第二半导体材料层来制造具有第一导电类型的砷化镓衬底的半导体激光器的方法, 组成InyGa1-yAs在第一层。 该层在半导体结构中经历足够的应变,以便使阈值电流密度最小化。 通过在第二层上沉积具有组成Al x Ga 1-x As和第二导电类型的第三层半导体材料并在第三层上沉积具有组成为GaAs并具有第二导电类型的第四层半导体材料来完成该器件。

    OPTICAL RING NETWORK
    65.
    发明申请
    OPTICAL RING NETWORK 审中-公开
    光环网络

    公开(公告)号:WO1987004029A1

    公开(公告)日:1987-07-02

    申请号:PCT/US1986002155

    申请日:1986-10-14

    CPC classification number: H04B10/27 H04B10/275

    Abstract: An optical-fiber ring network is capable of operating in the face of the failure of any single node regardless of the particular node failure mechanism, including stuck "on" and stuck "off" transmitters. Each node in the network (302) comprises a main receiver (312), an alternate receiver (322), and a transmitter (332). The main receiver (312) receives data from the immediately adjacent upstream node (301), while the alternate receiver (322) monitors transmissions from the next preceding upstream node. Each node diagnoses the transmitter in its immediately adjacent upstream neighbour and its own main receiver. If either fails, the node switches from its main receiver to its alternate receiver to bypass the immediately adjacent upstream node, while the rest of the ring remains functional.

    SYSTEM AND METHOD FOR EQUALIZING DELAY IN A DYNAMIC PACKET SWITCHING NETWORK
    66.
    发明申请
    SYSTEM AND METHOD FOR EQUALIZING DELAY IN A DYNAMIC PACKET SWITCHING NETWORK 审中-公开
    用于在动态分组交换网络中均衡化延迟的系统和方法

    公开(公告)号:WO1998053577A1

    公开(公告)日:1998-11-26

    申请号:PCT/US1997008688

    申请日:1997-05-22

    Abstract: A system and method for equalizing delay in a dynamic packet switching network using transmit and receive buffers. The network includes a plurality of user access stations each equipped with a transmit buffer (TB1, TB2) and a receive buffer (RB1, RB2), and plurality of switches (Sc) and communication links interconnecting the user access stations (UAS1, UAS2). A control station (CC1) having communication links to the switches (Sc) and user access stations (UAS1) operates to set up and change transmission paths between the user access stations, and to control the buffers in the user access stations to equalize packet transmission delay through the network and to eliminate packet rate doubling upon changing transmission paths. The system also includes a buffer shifting feature whereby a controlled buffering in a transmitting user access station is gradually shifted to a buffer in a receiving user access station during a period of time following a change from a longer transmission path to a shorter transmission path.

    Abstract translation: 一种使用发送和接收缓冲器来均衡动态分组交换网络中的延迟的系统和方法。 网络包括各自配备有发送缓冲器(TB1,TB2)和接收缓冲器(RB1,RB2)的多个用户接入站以及将用户接入站(UAS1,UAS2)互连的多个交换机(Sc)和通信链路, 。 具有到交换机(Sc)和用户接入站(UAS1)的通信链路的控制站(CC1)操作以建立和改变用户接入站之间的传输路径,并且控制用户接入站中的缓冲器以均衡分组传输 通过网络延迟,并且在改变传输路径时消除分组速率倍增。 该系统还包括缓冲移位特征,由此在从更长的传输路径到更短的传输路径的改变之后的时间段内,在发送用户接入站中的受控缓冲逐渐移动到接收用户接入站中的缓冲区。

    TERNARY CAM MEMORY ARCHITECTURE AND METHODOLOGY
    68.
    发明申请
    TERNARY CAM MEMORY ARCHITECTURE AND METHODOLOGY 审中-公开
    三次CAM记忆体结构与方法学

    公开(公告)号:WO1998007160A2

    公开(公告)日:1998-02-19

    申请号:PCT/US1997013216

    申请日:1997-07-29

    CPC classification number: G06F17/30982 G11C15/04

    Abstract: The present invention encompasses a method of storing ternary data that includes the steps of (1) initializing a conversion register by storing binary-to-ternary mask data in a conversion register; (2) storing ternary data in a content addressable memory (CAM) by inputting a single bit binary data to the conversion register, and converting the binary data into two bits of ternary data using the conversion register; and (3) simultaneously storing the two bits of ternary data in first and second memory cells. For subsequent searching, the method further includes the steps of searching for a match of input search binary data to the stored contents of the CAM; providing a match valid output responsive to the input search binary bits matching any of the stored contents; and generating an address corresponding to a location in the CAM where the match is found.

    Abstract translation: 本发明包括一种存储三进制数据的方法,包括以下步骤:(1)通过将二进制到三进制掩码数据存储在转换寄存器中来初始化转换寄存器; (2)通过向转换寄存器输入单位二进制数据,并且使用转换寄存器将二进制数据转换成三位数据,将三进制数据存储在内容可寻址存储器(CAM)中; 和(3)在第一和第二存储器单元中同时存储三位数据的两位。 为了后续搜索,该方法还包括以下步骤:搜索输入搜索二进制数据与CAM的存储内容的匹配; 提供响应于匹配任何存储的内容的输入搜索二进制位的匹配有效输出; 并且生成与CAM中找到匹配的位置相对应的地址。

    SYSTEM AND METHODS FOR PROVIDING VIDEOCONFERENCING SERVICES
    69.
    发明申请
    SYSTEM AND METHODS FOR PROVIDING VIDEOCONFERENCING SERVICES 审中-公开
    用于提供视频服务的系统和方法

    公开(公告)号:WO1997049243A1

    公开(公告)日:1997-12-24

    申请号:PCT/US1996010567

    申请日:1996-06-19

    CPC classification number: H04N7/17318 H04N7/15

    Abstract: A video conferencing system, comprising a broadband switch network (100), a plurality of video cameras (120), one video (120) corresponding to each of a plurality of videoconferencing parties, a plurality of controllers (110), one controller (110) corresponding to each video camera (120), a broadband session controller (104) for communicating with each of said controllers (110), and a broadband service control point (106) connected to said broadband session controller (104).

    Abstract translation: 一种视频会议系统,包括宽带交换网络(100),与多个视频会议方中的每一个对应的多个摄像机(120),一个视频(120),多个控制器(110),一个控制器 ),用于与每个所述控制器(110)通信的宽带会话控制器(104)以及连接到所述宽带会话控制器(104)的宽带服务控制点(106)。

    METHOD AND APPARATUS FOR INTEGRATION TELEPHONE AND BROADBAND NETWROKS
    70.
    发明申请
    METHOD AND APPARATUS FOR INTEGRATION TELEPHONE AND BROADBAND NETWROKS 审中-公开
    用于集成电话和宽带网络的方法和装置

    公开(公告)号:WO1997049223A1

    公开(公告)日:1997-12-24

    申请号:PCT/US1996010569

    申请日:1996-06-19

    Abstract: An integrated broadband/telephone service control point (1704) connected to both a broadband network (1700) and a telephone network (1702), comprising a first database (304) having a plurality of broadband processing records (306), a second database (1902) having a plurality of call processing records (1904), a system responsive to a first set of triggers from the broadband network (1700) for executing one or more of the broadband processing records (306) and returning (124) processing instructions to the broadband network (1700), and a system responsive to a second set of triggers from the telephone network (1702) for executing one or more of the call processing records (1904) and returning (124) processing instructions to the telephone network (1702).

    Abstract translation: 连接到宽带网络(1700)和电话网络(1702)的综合宽带/电话业务控制点(1704),包括具有多个宽带处理记录(306)的第一数据库(304),第二数据库 1902),具有多个呼叫处理记录(1904)的系统,响应于来自宽带网络(1700)的第一组触发器的系统,用于执行一个或多个宽带处理记录(306)和返回(124)处理指令, 所述宽带网络(1700)和响应于来自所述电话网络(1702)的第二组触发的系统用于执行所述呼叫处理记录(1904)中的一个或多个并且将所述处理指令返回(124)到所述电话网络(1702) )。

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