公开(公告)号：WO1998012651A1

公开(公告)日：1998-03-26

申请号：PCT/US1997014979

申请日：1997-08-25

Applicant: MOTOROLA INC. ,  BELL COMMUNICATIONS RESEARCH

Inventor： MOTOROLA INC. ,  BELL COMMUNICATIONS RESEARCH ,  KEMPKE, Robert, Alan ,  MCAULEY, Anthony, J. ,  LAMACCHIA, Michael, Philip

IPC: G06F17/30

CPC classification number: G06F17/30982 ,  G11C15/00

Abstract: A system for a pipeline cascaded content addressable memory CAM system for sequentially processing input data includes an input register, a CAM core, cascade logic and an output register. As the memory association functions produce matches in the CAM core, the cascade logic in parallel composites data associated with each matching CAM core. Each cascade processes a separate data input simultaneously then passes on the cumulative results to the next stage.

Abstract translation: 用于顺序处理输入数据的用于管线级联内容可寻址存储器CAM系统的系统包括输入寄存器，CAM内核，级联逻辑和输出寄存器。 由于存储器关联功能在CAM内核中产生匹配，所以级联逻辑并行复合数据与每个匹配的CAM内核相关联。 每个级联同时处理单独的数据输入，然后将累积结果传递到下一个阶段。

公开(公告)号：WO1998007160A2

公开(公告)日：1998-02-19

申请号：PCT/US1997013216

申请日：1997-07-29

Applicant: MOTOROLA INC. ,  BELL COMMUNICATIONS RESEARCH

Inventor： MOTOROLA INC. ,  BELL COMMUNICATIONS RESEARCH ,  KEMPKE, Robert, A. ,  MCAULEY, Anthony, J.

IPC: G11C11/56

CPC classification number: G06F17/30982 ,  G11C15/04

Abstract: The present invention encompasses a method of storing ternary data that includes the steps of (1) initializing a conversion register by storing binary-to-ternary mask data in a conversion register; (2) storing ternary data in a content addressable memory (CAM) by inputting a single bit binary data to the conversion register, and converting the binary data into two bits of ternary data using the conversion register; and (3) simultaneously storing the two bits of ternary data in first and second memory cells. For subsequent searching, the method further includes the steps of searching for a match of input search binary data to the stored contents of the CAM; providing a match valid output responsive to the input search binary bits matching any of the stored contents; and generating an address corresponding to a location in the CAM where the match is found.

Abstract translation: 本发明包括一种存储三进制数据的方法，包括以下步骤：（1）通过将二进制到三进制掩码数据存储在转换寄存器中来初始化转换寄存器; （2）通过向转换寄存器输入单位二进制数据，并且使用转换寄存器将二进制数据转换成三位数据，将三进制数据存储在内容可寻址存储器（CAM）中; 和（3）在第一和第二存储器单元中同时存储三位数据的两位。 为了后续搜索，该方法还包括以下步骤：搜索输入搜索二进制数据与CAM的存储内容的匹配; 提供响应于匹配任何存储的内容的输入搜索二进制位的匹配有效输出; 并且生成与CAM中找到匹配的位置相对应的地址。

公开(公告)号：WO1997041708A3

公开(公告)日：1997-11-06

申请号：PCT/US1997006311

申请日：1997-04-15

Applicant: MOTOROLA INC. ,  BELL COMMUNICATIONS RESEARCH

Inventor： MOTOROLA INC. ,  BELL COMMUNICATIONS RESEARCH ,  THOMPSON, Horace, C. ,  FELDMEIER, David, C. ,  MARCUS, William, S.

IPC: H04Q11/04

公开(公告)号：WO1986006231A1

公开(公告)日：1986-10-23

申请号：PCT/US1985001617

申请日：1985-08-26

Applicant: BELL COMMUNICATIONS RESEARCH

Inventor： BELL COMMUNICATIONS RESEARCH ,  WALTERS, Stephen, Madison

IPC: H04J03/16

CPC classification number: H04J3/1629

Abstract: In order to multiplex a plurality of various rate subchannels onto a fixed rate channel, a frame structure is defined consisting of j sets of i-tuples for a total of ij bits per frame, the parameters i and j being mathematically determined as a function of the rate of the subchannels and the rate of the fixed channel. For j-1 of the i-tuples, i-1 bits are used for information and the last bit is set ONE. In one i-tuple all i bits are set ZERO. Framing is detected by monitoring for a ONE followed by i ZEROes, a pattern which cannot occur elsewhere in the frame regardless of the data. An integral number of information bits from each subchannel are distributed in the (i-1) (j-1) information bit positions. In the disclosed embodiment two 666-2/3 bps channels and a 4800 bps channel are multiplexed onto an 8000 bps channel using a frame structure consisting of 24 quintets. In the 92 information bit positions, 72 bits are allocated for the 4800 bps channel and 10 bits each are allocated for the 666-2/3 bps channels. The multiplexer shifts the input bits through shift registers (403, 404, 406) and selects (407) for output at the 8000 bps rate one of the stored input bits or a set ONE or ZERO as determined by a sequencer (410). The demultiplexer shifts the bits in the multiplexed bit streams through a shift register (802) and selects (814) as determined by a sequencer (813) appropriate stored bits for output in the demultiplexed bit streams. Framing is maintained by a pattern detector (804) which is responsive to only a ONE followed by five ZEROes in the multiplexed stream.