公开(公告)号：EP2720267A1

公开(公告)日：2014-04-16

申请号：EP13188322.5

申请日：2013-10-11

Applicant: J-Devices Corporation

Inventor： Itakura, Satoru ,  Katsumata, Akio ,  Umeki, Akihiro ,  Shiraishi, Yasushi ,  Abe, Junichiro

IPC: H01L25/10 ,  H01L25/065 ,  H01L25/18 ,  G06F3/00

CPC classification number: G11C16/30 ,  G06F3/00 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1069 ,  G11C11/4096 ,  H01L22/10 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/19105

Abstract: A semiconductor storage device (100) includes a controller package (110) having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages (120) each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.

Abstract translation: 半导体存储装置（100）包括在其底面上具有BGA端子的控制器封装（110） 以及一个或多个存储器封装（120），每个存储器封装（120）包括多个半导体存储元件并且安装在所述控制器封装上。 所述控制器封装包括在其底表面上具有所述BGA端子的底部基板; 电源IC，安装在底部基板上，用于供给多个电源; 以及控制器，其安装在所述底部基板上并且可由所述电源IC提供的所述多个电源操作。 控制器通过BGA终端提供与外部系统的接口，并控制来自半导体存储元件的读取操作和对半导体存储元件的写入操作。

公开(公告)号：EP2634796B1

公开(公告)日：2020-04-08

申请号：EP12189403.4

申请日：2012-10-22

Applicant: J-Devices Corporation

Inventor： Sawachi, Shigenori ,  Yamagata, Osamu ,  Inoue, Hiroshi ,  Itakura, Satoru ,  Chikai, Tomoshige ,  Hori, Masahiko ,  Katsumata, Akio

IPC: H01L23/538 ,  H01L21/98

公开(公告)号：EP2733729A3

公开(公告)日：2016-09-21

申请号：EP13193352.5

申请日：2013-11-18

Applicant: J-Devices Corporation

Inventor： Suda, Toru

IPC: H01L21/56 ,  H01L21/60 ,  H01L25/065 ,  H01L21/98 ,  H01L23/498 ,  H01L23/31 ,  H01L23/14

CPC classification number: H01L23/3157 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/556 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/11462 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a rectangular lower semiconductor element (6); a plurality of external electrodes (9) located in a pattern on the lower semiconductor element along sides thereof; a plurality of internal electrodes electrically connected to the plurality of external electrodes via a plurality of line patterns respectively and located on the lower semiconductor element in a pattern; dams (12) provided in such a pattern that each of the dams encloses one or at least two external electrodes among the plurality of external electrodes; an upper semiconductor element (5) mounted on the lower semiconductor element (6) such that a plurality of terminals on the upper semiconductor element are electrically connected to the plurality of internal electrodes respectively; and a resin (4) potted to flow to a space between the lower semiconductor element and the upper semiconductor element.

公开(公告)号：EP2733729A2

公开(公告)日：2014-05-21

申请号：EP13193352.5

申请日：2013-11-18

Applicant: J-Devices Corporation

Inventor： Suda, Toru

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3157 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/556 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/11462 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a rectangular lower semiconductor element (6); a plurality of external electrodes (9) located in a pattern on the lower semiconductor element along sides thereof; a plurality of internal electrodes electrically connected to the plurality of external electrodes via a plurality of line patterns respectively and located on the lower semiconductor element in a pattern; dams (12) provided in such a pattern that each of the dams encloses one or at least two external electrodes among the plurality of external electrodes; an upper semiconductor element (5) mounted on the lower semiconductor element (6) such that a plurality of terminals on the upper semiconductor element are electrically connected to the plurality of internal electrodes respectively; and a resin (4) potted to flow to a space between the lower semiconductor element and the upper semiconductor element.

Abstract translation: 半导体器件包括矩形下半导体元件（6）; 多个外部电极（9），沿其侧面位于下部半导体元件上的图案中; 多个内部电极经由多个线图案电连接到多个外部电极，并以图案位于下部半导体元件上; 堤坝（12）以这样的图案提供，使得每个坝围绕多个外部电极中的一个或至少两个外部电极; 安装在下半导体元件（6）上的上半导体元件（5），使得上半导体元件上的多个端子分别电连接到多个内部电极; 和封装在下半导体元件与上半导体元件之间的空间的树脂（4）。

公开(公告)号：EP2551904A1

公开(公告)日：2013-01-30

申请号：EP12177861.7

申请日：2012-07-25

Applicant: J-Devices Corporation

Inventor： Yamagata, Osamu ,  Katsumata, Akio ,  Inoue, Hiroshi ,  Sawachi, Shigenori ,  Itakura, Satoru ,  Yamaji, Yasuhiro

IPC: H01L25/10

CPC classification number: H01L24/97 ,  H01L24/19 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/0951 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1579 ,  H01L2924/15798 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device, comprising: an organic substrate 1; through vias 4 which penetrate the organic substrate 1 in its thickness direction; external electrodes 5b and internal electrodes 5a provided to the front and back faces of the organic substrate 1 and electrically connected to the through vias 4; a semiconductor element mounted on one main surface of the organic substrate 1 via a bonding layer 3, with an element circuit surface thereof facing upward; an insulating material layer 6 for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer 7 provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias 10 provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes 9 formed on the metal thin film wiring layer 7, wherein the metal thin film wiring layer 7 is structured such that the electrodes disposed on the element circuit surface of the semiconductor element 2, the internal electrodes 5a, the metal vias 10, and the external electrodes 9 formed on the metal thin film wiring layer are electrically connected.

Abstract translation: 一种半导体装置，包括：有机衬底1; 通过该穿透在其厚度方向上的有机基板1的通孔4; 外部电极5b和提供到有机衬底的正面和背面内部电极5a 1和电连接到通孔4; 半导体元件通过粘接层3安装在有机衬底1的一个主表面上，在元件电路表面朝上; 绝缘材料层6，用于将半导体元件和其周边密封的; 在绝缘材料层中，与外表面被暴露在该金属薄膜布线层的一部分的金属薄膜布线层7; 提供在绝缘材料层10和电连接到所述金属薄膜布线层金属通路; 和外部电极9形成的金属薄膜布线层7上，worin金属薄膜布线层7的结构搜索，设置在半导体元件2的元件电路表面上DASS模电极，所述内部电极5a，金属过孔10， 和形成在所述金属薄膜布线层的外部电极9电连接。

公开(公告)号：US10224256B2

公开(公告)日：2019-03-05

申请号：US15625464

申请日：2017-06-16

Applicant: J-DEVICES CORPORATION

Inventor： Hirokazu Machida ,  Kazuhiko Kitano

IPC: H01L21/48 ,  H01L23/14 ,  H01L21/56 ,  H01L23/31 ,  H01L23/544 ,  H01L23/552 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

Abstract: A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.

公开(公告)号：US09635762B2

公开(公告)日：2017-04-25

申请号：US14803889

申请日：2015-07-20

Applicant: J-DEVICES CORPORATION

Inventor： Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Hiroshi Demachi ,  Takeshi Miyakoshi ,  Tomoshige Chikai ,  Kiminori Ishido ,  Hiroaki Matsubara ,  Takashi Nakamura ,  Hirokazu Honda ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/02 ,  H01L23/10 ,  H05K1/18 ,  H01L23/367 ,  H05K1/02 ,  H01L25/10 ,  H01L23/36 ,  H01L23/373 ,  H01L23/433 ,  H01L23/498 ,  H01L23/31

CPC classification number: H05K1/181 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15331 ,  H01L2924/1815 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/141 ,  H05K2201/0275 ,  H05K2201/066 ,  H05K2201/10515 ,  H05K2203/1311 ,  H05K2203/1322 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

公开(公告)号：US09595488B2

公开(公告)日：2017-03-14

申请号：US15010988

申请日：2016-01-29

Applicant: J-DEVICES CORPORATION

Inventor： Yoshihiro Tanaka

IPC: H01L23/52 ,  H01L29/40 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/49513 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/26175 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29078 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83815 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device according to one embodiment of the present invention includes a semiconductor element, an island having a surface on which the semiconductor element is fixed using a first metal, and a first pattern formed by a second metal, the first pattern being arranged on one part of the surface, wherein the second metal has a greater wetting characteristic than the surface when the first metal is melted.

Abstract translation: 根据本发明的一个实施例的半导体器件包括半导体元件，具有使用第一金属固定半导体元件的表面的岛和由第二金属形成的第一图案，第一图案被布置在一个上 表面的一部分，其中当第一金属熔化时，第二金属具有比表面更大的润湿特性。

公开(公告)号：US09553052B2

公开(公告)日：2017-01-24

申请号：US14963970

申请日：2015-12-09

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Toshihiro Iwasaki ,  Tomoshige Chikai ,  Kiminori Ishido ,  Shinji Watanabe ,  Michiaki Tamakawa

IPC: H01L29/82 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Abstract translation: 一种非易失性磁存储元件的磁屏蔽封装，包括：软磁材料支撑板12; 形成在支撑板上的第一绝缘材料层13; 固定在第一绝缘材料层上的非易失性磁存储元件11; 封装存储元件及其周边的第二绝缘材料层14; 在第二绝缘材料层中，布线层15，软磁性层15b或25以及连接存储元件的电路表面的电极和布线层的导电部分16; 以及磁屏蔽部17，所述磁屏蔽部17包含与存储元件的侧面隔开一定距离地配置的软磁性材料，以便部分地或全部地包围存储元件侧表面，所述磁屏蔽部磁性地连接到软磁 层。

公开(公告)号：US20160181194A1

公开(公告)日：2016-06-23

申请号：US14964121

申请日：2015-12-09

Applicant: J-Devices Corporation

Inventor： Yoshihiko IKEMOTO ,  Shigenori SAWACHI ,  Fumihiko TANIGUCHI ,  Akio KATSUMATA

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/3142 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5227 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267

Abstract: The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the Q value of the RF circuit of the semiconductor device is improved even using the metal flat plate as a support.

Abstract translation: 本发明提供一种半导体器件，其中金属平板中的涡电流的产生减小，并且即使使用金属平板作为支撑件，也提高了半导体器件的RF电路的Q值。