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    Method of forming resist pattern and semiconductor device manufactured with the same
    62.
    发明公开
    Method of forming resist pattern and semiconductor device manufactured with the same 审中-公开
    形成抗蚀剂图案的方法和用其制造的半导体器件

    公开(公告)号：EP1975719A2

    公开(公告)日：2008-10-01

    申请号：EP08005983.5

    申请日：2008-03-28

    Applicant: Renesas Technology Corp.

    Inventor： Ishibashi, Takeo ,  Terai, Mamoru ,  Hagiwara, Takuya ,  Yamaguchi, Atsumi

    IPC: G03F7/11 ,  G03F7/20 ,  G03F7/09 ,  G03F7/16

    CPC classification number: G03F7/2041 ,  G03F7/11 ,  Y10T428/24835

    Abstract: A method of forming a resist pattern through liquid immersion exposure in which exposure is performed such that a liquid film is formed between a substrate for a semiconductor device on which a processed film is formed and an objective lens arranged above the substrate is provided, and the substrate treated with a water-repellent agent solution composed of at least a water-repellent agent and a solvent is exposed to light.

    Abstract translation: 一种通过液浸曝光形成抗蚀剂图案的方法，其中进行曝光以使得在形成有处理过的膜的半导体器件用基板和布置在基板上方的物镜之间形成液膜，并且 用至少包含防水剂和溶剂的防水剂溶液处理过的基材暴露于光下。

    Nonvolatile semiconductor memory device and method of producing the same
    65.
    发明公开
    Nonvolatile semiconductor memory device and method of producing the same 审中-公开
    NichtflüchtigesHalbleiterspeicherbauelement und Verfahren zur Herstellung davon

    公开(公告)号：EP1916710A1

    公开(公告)日：2008-04-30

    申请号：EP07020815.2

    申请日：2007-10-24

    Applicant: Renesas Technology Corp.

    Inventor： Ishii, Motoharu ,  Sakakibara, Kiyohiko

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate (SB) having a principal surface, memory transistors (MT), and selection transistors (ST). Each of the memory transistors (MT) has a floating gate (FG) and a control gate (CG) that are formed by lamination with each other on the principal surface. Each of the selection transistors (ST) has a lower gate layer (G2) and an upper gate layer (G1) that are formed by lamination with each other on the principal surface, and is contained in a memory cell (MC) together with one of the memory transistors (MS). The lower gate layer (G2) is separated for each one of the selection transistors (ST). The upper gate layer (G1) is owned commonly by the selection transistors (ST) and is electrically connected to the lower gate layer (G2) of each of the selection transistors (ST). Therefore, it is possible to prevent short-circuiting of the selection transistors (ST) and the memory transistors (MT).

    Abstract translation: 非易失性半导体存储器件包括具有主表面的半导体衬底（SB），存储晶体管（MT）和选择晶体管（ST）。 每个存储晶体管（MT）具有通过在主表面上彼此叠层形成的浮栅（FG）和控制栅（CG）。 每个选择晶体管（ST）具有通过在主表面上彼此层叠而形成的下栅极层（G2）和上栅极层（G1），并且与一个存储单元（MC）一起包含在存储单元 的存储晶体管（MS）。 对于选择晶体管（ST）中的每一个分离下栅极层（G2）。 上栅极层（G1）由选择晶体管（ST）共同拥有，并且电连接到每个选择晶体管（ST）的下栅极层（G2）。 因此，可以防止选择晶体管（ST）和存储晶体管（MT）的短路。

    MEMORY CARD AND CARD ADAPTER
    66.
    发明公开
    MEMORY CARD AND CARD ADAPTER 有权
    SPEICHERKARTE UND KARTENADAPTER

    公开(公告)号：EP1883041A1

    公开(公告)日：2008-01-30

    申请号：EP06746547.6

    申请日：2006-05-17

    Applicant: Sony Corporation ,  Renesas Technology Corp.

    Inventor： AOKI, Yoshitaka ,  TSUTSUI, Keiichi ,  NISHIZAWA, Hirotaka, c/o RENESAS TECHNOLOGY CORP. ,  TOTSUKA, Takashi, c/o RENESAS TECHNOLOGY CORP.

    IPC: G06K19/07 ,  G06F3/08 ,  G06K17/00

    CPC classification number: G06K19/07 ,  G06K19/07732

    Abstract: There is provided a memory card usable with a selected one of a plurality of interfaces. The memory card (100) includes a holder (20), a memory unit (22) buried in the holder (20), a controller (24) buried in the holder (20), a plurality of first contacts (2 to 10) connected to the controller (24), a select signal generator (26) buried in the holder (20) and two second contacts (11, 12) connected to the select signal generator (26). The select signal generator (26) is to supply a select signal S1 to an interface unit (2402) correspondingly to interface select signals D1 and D2 supplied via the second contacts. One of two types of interfaces is selected based on the interface select signal S1 supplied via the second contacts and data communication is made via the selected interface.

    Abstract translation: 提供了可与多个接口中选择的一个接口使用的存储卡。 存储卡（100）包括保持器（20），埋在保持器（20）中的存储单元（22），埋在保持器（20）中的控制器（24），多个第一触点（2至10） 连接到控制器（24），埋入保持器（20）中的选择信号发生器（26）和连接到选择信号发生器（26）的两个第二触点（11,12）。 选择信号发生器26将对应于经由第二触点提供的接口选择信号D1和D2向接口单元2402提供选择信号S1。 基于经由第二接点提供的接口选择信号S1选择两种类型的接口之一，并且经由所选择的接口进行数据通信。

    PLL circuit and radio communication terminal apparatus using the same
    67.
    发明公开
    PLL circuit and radio communication terminal apparatus using the same 有权
    PLL Schaltung undFunkendgerät，das selbige benutzt

    公开(公告)号：EP1758255A2

    公开(公告)日：2007-02-28

    申请号：EP06017995.9

    申请日：1999-09-14

    Applicant: Renesas Technology Corp. ,  TTPCOM Limited

    Inventor： Yamawaki, Taizo, c/o Hitachi, Ltd. ,  Endo, Takefumi, c/o Hitachi, Ltd. ,  Watanabe, Kazuo, c/o Hitachi, Ltd. ,  Hori, Kazuaki, c/o Hitachi, Ltd. ,  Hildersley, Julian, c/o TTPCom Limited

    IPC: H04B1/40 ,  H03L7/08

    CPC classification number: H03L7/10 ,  H03D13/007 ,  H03L7/08 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/12 ,  H04B1/406

    Abstract: A PLL circuit and a radio communication terminal apparatus using the PLL circuit is provided. In the PLL circuit, the number of n pieces of LPFs which have been required is reduced to only one LPF, so that the PLL circuit can reduce a mounting area and the number of pins, and can simplify its design. The PLL circuit according to the present invention comprises a variable-gain phase comparator 1, a mixer 2, an LPF 3, n pieces of VCOs 4-1 to 4n, n pieces of couplers 5-1 to 5-n, and a control circuit 6 for controlling the on/off of the operation of the VCOs. The variable-gain phase comparator 1 is a phase comparator capable of varying a phase difference gain. By the control circuit 6, the on/off of the operation of the VCOs 4-1 to 4n and one of the VCOs 4-1 to 4-n is operated in accordance with a desired operation frequency band; other VCOs are controlled to an off state. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs 4-1 to 4-n, and thereby, the number of LPF required for the PLL circuit can be reduced to only one.

    Abstract translation: 提供了PLL电路和使用PLL电路的无线通信终端装置。 在PLL电路中，已经需要的n个LPF的数量减少到仅一个LPF，使得PLL电路可以减少安装面积和引脚数量，并且可以简化其设计。 根据本发明的PLL电路包括可变增益相位比较器1，混频器2，LPF 3，n个VCO 4-1至4n，n个耦合器5-1至5-n，以及控制 电路6，用于控制VCO的操作的开/关。 可变增益相位比较器1是能够改变相位差增益的相位比较器。 通过控制电路6，根据期望的工作频带来操作VCO 4-1至4n和VCO 4-1至4-n中的一个的操作的导通/截止; 其他VCO被控制为关闭状态。 相位差转换增益根据VCO 4-1至4-n的灵敏度而变化，从而可将PLL电路所需的LPF数减少到仅一个。

    Memory card adaptor
    68.
    发明公开
    Memory card adaptor 审中-公开

    公开(公告)号：EP1748380A2

    公开(公告)日：2007-01-31

    申请号：EP06014151.2

    申请日：2006-07-07

    Applicant: SONY CORPORATION ,  Renesas Technology Corp.

    Inventor： Aoki, Yoshitaka ,  Tsutsui, Keiichi ,  Nishizawa, Hirotaka ,  Totsuka, Takashi

    IPC: G06K19/077

    CPC classification number: G06K19/077 ,  G06K19/07739 ,  Y10S439/945

    Abstract: A card tray to be mounted to a memory card can make the memory card mountable in a card slot for memory cards conforming to standards different from those to which the memory card conforms. The card tray has a main body and a recessed mount section. The recessed mount section is formed such that the holder of a second memory card can be mounted to one of the major surfaces of the main body. A memory-card-mounted body is produced when the second memory card is mounted to the recessed mount section. The card tray is configured such that, when the first memory card is placed on the memory-card-mounted body with the left and right edges thereof aligned with each other, the contact pieces of the first memory card and the contact pieces of the second memory card have longitudinally overlapping parts and transversally overlapping parts as viewed from above.

    FILM FORMING DEVICE AND FILM FORMING METHOD
    69.
    发明公开
    FILM FORMING DEVICE AND FILM FORMING METHOD 审中-公开
    FILMERZEUGUNGSEINRICHTUNG UND FILMERZEUGUNGSVERFAHREN

    公开(公告)号：EP1705699A1

    公开(公告)日：2006-09-27

    申请号：EP04807596.4

    申请日：2004-12-22

    Applicant: HORIBA, LTD. ,  Renesas Technology Corp. ,  ROHM CO., LTD.

    Inventor： TOMINAGA, Koji ,  YASUDA, Tetsuji ,  NABATAME, Toshihide ,  IWAMOTO, Kunihiko

    IPC: H01L21/205 ,  C23C16/455

    CPC classification number: C23C16/45527 ,  C23C16/45531 ,  C23C16/45544

    Abstract: A throughput during a process of forming a thin film is improved and a thin film of high quality is produced at low cost.
    For this purpose, a film forming system comprises a chamber 8, a precursory gas supplying line 2 to supply the chamber 8 with precursory gas, a reactive gas supplying line 1 to supply the chamber 8 with reactive gas, and a purge gas supplying line 3 to supply purge gas that purges the precursory gas and the reactive gas, and forms a thin film on a substrate 82 in the chamber 8 by supplying the precursory gas or the reactive gas and purging alternately, and further comprises a middle line 22 having a certain volume that is arranged on a part or all of the precursor supplying line 2 and into which the precursory gas can be filled at a time when the precursory gas is not supplied, and/or a middle line 12 having a certain volume that is arranged on a part or all of the reactive gas supplying line 1 and into which the reactive gas can be filled at a time when the reactive gas is not supplied.

    Abstract translation: 在薄膜形成过程中的生产量得到改善，并且以低成本生产高质量的薄膜。 为此，成膜系统包括：室8，用于向室8供应前兆气体的前体气体供应管线2;向反应气体供应反应气体的反应气体供应管线1;以及吹扫气体供应管线3 以提供清除前体气体和反应性气体的吹扫气体，并且通过供应前体气体或反应性气体并交替进行吹扫而在室8中的基板82上形成薄膜，并且还包括具有一定的中间线22的中间线22 配置在前体供给管线2的一部分或全部的体积，并且在不供给前体气体的时候可以填充前体气体的体积，和/或具有一定体积的中间线12布置在 反应气体供应管线1的一部分或全部，并且在反应气体不被供应的时候可以填充反应气体。

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