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    Repairable memory circuit
    62.
    发明公开
    Repairable memory circuit 失效
    Reparierbare Speicherschaltung。

    公开(公告)号：EP0434200A1

    公开(公告)日：1991-06-26

    申请号：EP90311876.8

    申请日：1990-10-30

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Ferris, Andrew Timothy ,  Work, Gordon Stirling

    IPC: G06F11/20

    CPC classification number: G11C29/848

    Abstract: A memory circuit comprises a memory array (1) having a plurality of memory cells arranged in rows and columns;
    a plurality of column select circuits (CS₀-CS₇) for enabling access to columns in said array, each column select circuit being associated with a respective group of said columns and being arranged to access a selected one of the columns in the respective group;
    at least one spare memory column (14);
    a plurality of read/write circuits (R/W₀-R/W₇) associated respectively with the said groups, and with said spare column, for reading or writing data bits between the data bus and the columns selected by the column select circuits; and
    routing circuitry (8) connected between the read/write circuits and the data bus and being programmable with information identifying at least one faulty column, the routing circuitry being operable in response to an attempted access to said faulty column to disconnect from the data bus the read/write circuit associated with the group containing the faulty column and to connect to the data bus the read/write circuit associated with the spare column thereby to transfer data between said spare column and the data bus.

    Abstract translation: 存储器电路包括具有以行和列排列的多个存储器单元的存储器阵列（1） 多个列选择电路（CS0-CS7），用于使得能够访问所述阵列中的列，每个列选择电路与相应的所述列组相关联，并被布置成访问相应组中的所选列中的一个; 至少一个备用存储器列（14）; 分别与所述组相关联的多个读/写电路（R / W0-R / W7）和所述备用列，用于在数据总线和由列选择电路选择的列之间读取或写入数据位; 以及连接在所述读/写电路和所述数据总线之间并且可识别至少一个故障列的信息的路由电路（8），所述路由电路可响应于对所述故障列的尝试访问而与所述数据总线断开连接 与包含故障列的组相关联的读/写电路，并且与数据总线连接与备用列相关联的读/写电路，从而在所述备用列和数据总线之间传送数据。

    Memory cell
    63.
    发明公开
    Memory cell 失效
    记忆体

    公开(公告)号：EP0278587A3

    公开(公告)日：1991-01-23

    申请号：EP88300098.6

    申请日：1988-01-07

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Campbell, Richard Norman ,  Edwards, Jonathan ,  Thompson, Michael Kevin

    IPC: H01L27/11 ,  G11C11/412

    CPC classification number: H01L27/1112 ,  G11C11/412

    Abstract: In a semi-conductor memory cell components are formed in regions separated from each other by one or more insulation layers (40) and first and second load resistors (20,22) and gate regions (70,72) of first and second cross-coupled driver field effect transistors (16,18) are formed in a first conductive layer (64) and the word line (36) and gate regions (66,68) of first and second transfer transistors (28,30) are formed in a second conductive layer (60).

    Fabricating electrical contacts in semiconductor devices
    64.
    发明公开
    Fabricating electrical contacts in semiconductor devices 失效
    Herstellung von elektrischen Kontakten auf Halbleiterbauelementen。

    公开(公告)号：EP0403050A2

    公开(公告)日：1990-12-19

    申请号：EP90302870.2

    申请日：1990-03-16

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Hunt, Paul Anthony ,  Liles, Ian Michael ,  Guite, David Ralph

    IPC: H01L21/285

    CPC classification number: H01L21/28 ,  H01L21/3105

    Abstract: A method of fabricating an electrical contact in a semiconductor device, the method comprising the steps of:-

    (a) providing on an underlying silicon substrate (2) a reflowable interlevel dielectric material (14) having a contact opening exposing a contact region of the silicon substrate;
    (b) heating the silicon substrate and the interlevel dielectric material by a rapid thermal anneal in an oxygen-containing atmosphere thereby to grow an oxide control layer (20) in the contact region and to reflow the dielectric material;
    (c) depositing a layer of transition metal (28) over the reflowed dielectric material and the control layer; and
    (d) converting at least part of the transition metal layer into a metallurgic barrier.

    Abstract translation: 一种在半导体器件中制造电接触的方法，所述方法包括以下步骤： - （a）在下面的硅衬底（2）上提供可回流层间电介质材料（14），所述可回流层间电介质材料具有暴露所述接触区域的接触区域 硅衬底; （b）通过在含氧气氛中的快速热退火来加热硅衬底和层间电介质材料，从而在接触区域中生长氧化物控制层（20）并回流电介质材料; （c）在所述回流的电介质材料和所述控制层上沉积过渡金属层（28）; 和（d）将至少部分过渡金属层转化成冶金屏障。 Ť

    A CACHE SYSTEM
    65.
    发明公开
    A CACHE SYSTEM 失效
    高速缓存再填充在一个动态的系统有红利CACHE的划分

    公开(公告)号：EP0890149A1

    公开(公告)日：1999-01-13

    申请号：EP98902083.0

    申请日：1998-01-29

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： STURGES, Andrew, Craig ,  MAY, David

    IPC: G06F12

    CPC classification number: G06F12/0804 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/1045

    Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

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