公开(公告)号：EP0391562B1

公开(公告)日：1997-01-08

申请号：EP90302869.4

申请日：1990-03-16

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Nicholls, Howard Charles ,  Norrington, Michael John ,  Thompson, Michael Kevin

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76877 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP0278587A2

公开(公告)日：1988-08-17

申请号：EP88300098.6

申请日：1988-01-07

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Campbell, Richard Norman ,  Edwards, Jonathan ,  Thompson, Michael Kevin

IPC: H01L27/11 ,  G11C11/412

CPC classification number: H01L27/1112 ,  G11C11/412

Abstract: In a semi-conductor memory cell components are formed in regions separated from each other by one or more insulation layers (40) and first and second load resistors (20,22) and gate regions (70,72) of first and second cross-coupled driver field effect transistors (16,18) are formed in a first conductive layer (64) and the word line (36) and gate regions (66,68) of first and second transfer transistors (28,30) are formed in a second conductive layer (60).

Abstract translation: 在半导体存储单元中，元件通过一个或多个绝缘层（40）和第一和第二横截面的第一和第二负载电阻（20,22）和栅极区（70,72）彼此分开形成， 耦合驱动器场效应晶体管（16,18）形成在第一导电层（64）中，并且第一和第二转移晶体管（28,30）的字线（36）和栅极区域（66,68）形成在 第二导电层（60）。

公开(公告)号：EP0278587A3

公开(公告)日：1991-01-23

申请号：EP88300098.6

申请日：1988-01-07

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Campbell, Richard Norman ,  Edwards, Jonathan ,  Thompson, Michael Kevin

IPC: H01L27/11 ,  G11C11/412

CPC classification number: H01L27/1112 ,  G11C11/412

Abstract: In a semi-conductor memory cell components are formed in regions separated from each other by one or more insulation layers (40) and first and second load resistors (20,22) and gate regions (70,72) of first and second cross-coupled driver field effect transistors (16,18) are formed in a first conductive layer (64) and the word line (36) and gate regions (66,68) of first and second transfer transistors (28,30) are formed in a second conductive layer (60).

公开(公告)号：EP0391562A3

公开(公告)日：1991-03-13

申请号：EP90302869.4

申请日：1990-03-16

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Nicholls, Howard Charles ,  Norrington, Michael John ,  Thompson, Michael Kevin

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76877 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a tungsten contact in a semiconductor device, which method comprises the steps of:-
(a) providing an oxide layer (34) on a region of a silicon substrate; (b) depositing a sealing dielectric layer (44) over the oxide layer; (c) depositing an interlevel dielectric layer (46) over the sealing layer; (d) etching through the interlevel dielectric layer, the sealing dielectric layer and the oxide layer as far as the substrate thereby to form a contact hole and to expose the said region; (e) implanting a dopant into the said region whereby the implanted dopant is self-aligned to the contact hole; (f) thermally annealing the substrate; (g) selectively depositing tungsten in the contact hole; and (h) depositing an interconnect layer over the deposited tungsten contact. The invention also provides a semiconductor device.

公开(公告)号：EP0391562A2

公开(公告)日：1990-10-10

申请号：EP90302869.4

申请日：1990-03-16

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Nicholls, Howard Charles ,  Norrington, Michael John ,  Thompson, Michael Kevin

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76877 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a tungsten contact in a semiconductor device, which method comprises the steps of:-

(a) providing an oxide layer (34) on a region of a silicon substrate;
(b) depositing a sealing dielectric layer (44) over the oxide layer;
(c) depositing an interlevel dielectric layer (46) over the sealing layer;
(d) etching through the interlevel dielectric layer, the sealing dielectric layer and the oxide layer as far as the substrate thereby to form a contact hole and to expose the said region;
(e) implanting a dopant into the said region whereby the implanted dopant is self-aligned to the contact hole;
(f) thermally annealing the substrate;
(g) selectively depositing tungsten in the contact hole; and
(h) depositing an interconnect layer over the deposited tungsten contact.

The invention also provides a semiconductor device.

Abstract translation: 一种在半导体器件中制造钨触点的方法，该方法包括以下步骤： - （a）在硅衬底的区域上提供氧化物层（34）; （b）在所述氧化物层上沉积密封电介质层（44）; （c）在所述密封层上沉积层间电介质层（46）; （d）通过层间电介质层，密封电介质层和氧化层蚀刻到基底上，从而形成接触孔并露出所述区域; （e）将掺杂剂注入所述区域，由此注入的掺杂剂与接触孔自对准; （f）对基板进行热退火; （g）在接触孔中选择性地沉积钨; 和（h）在沉积的钨触点上沉积互连层。 本发明还提供一种半导体器件。

公开(公告)号：EP0278587B1

公开(公告)日：1995-06-21

申请号：EP88300098.6

申请日：1988-01-07

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Campbell, Richard Norman ,  Edwards, Jonathan ,  Thompson, Michael Kevin

IPC: H01L27/11 ,  G11C11/412

CPC classification number: H01L27/1112 ,  G11C11/412

公开(公告)号：EP0289163A3

公开(公告)日：1991-02-06

申请号：EP88303253.4

申请日：1988-04-12

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Campbell, Richard Norman ,  Thompson, Michael Kevin ,  Smith, Elizabeth Ann

IPC: H01L27/13 ,  H01L21/90 ,  H01L21/31

CPC classification number: H01L28/24 ,  H01L21/0272 ,  H01L27/11 ,  H01L27/1112 ,  H01L28/20 ,  Y10S257/904

Abstract: A method of fabricating a polycide semiconductor element, the method including the steps of:-
(a) forming a lift-off mask on a first region of a layer of polysilicon; (b) implanting a first dopant into second regions of the polysilicon which are adjacent the first region, the first region being masked from implantation by the lift-off mask; (c) forming a layer of silicide over the implanted regions and the lift-off mask; and (d) removing the lift-off mask and the respective part of the layer of silicide which is formed thereover thereby to expose the first region. The invention also provides a semiconductor element.

公开(公告)号：EP0289163A2

公开(公告)日：1988-11-02

申请号：EP88303253.4

申请日：1988-04-12

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Campbell, Richard Norman ,  Thompson, Michael Kevin ,  Smith, Elizabeth Ann

IPC: H01L27/13 ,  H01L21/90 ,  H01L21/31

CPC classification number: H01L28/24 ,  H01L21/0272 ,  H01L27/11 ,  H01L27/1112 ,  H01L28/20 ,  Y10S257/904

Abstract: A method of fabricating a polycide semiconductor element, the method including the steps of:-

(a) forming a lift-off mask on a first region of a layer of polysilicon;
(b) implanting a first dopant into second regions of the polysilicon which are adjacent the first region, the first region being masked from implantation by the lift-off mask;
(c) forming a layer of silicide over the implanted regions and the lift-off mask; and
(d) removing the lift-off mask and the respective part of the layer of silicide which is formed thereover thereby to expose the first region. The invention also provides a semiconductor element.

Abstract translation: 一种制造多晶半导体元件的方法，所述方法包括以下步骤：（a）在多晶硅层的第一区域上形成剥离掩模; （b）将第一掺杂剂注入与所述第一区域相邻的所述多晶硅的第二区域中，所述第一区域被所述剥离掩模掩埋; （c）在所述注入区域和剥离掩模之上形成硅化物层; 以及（d）去除剥离掩模和形成在其上的硅化物层的相应部分，从而暴露第一区域。 本发明还提供一种半导体元件。 H